Analysis and modeling of submicron drain-offset polysilicon thin film transistors (TFTs)

John Damiano Jr.; Le-Tien Jung; Sanjay K. Banerjee; S. Batra; M. Manning; C. Dennison

doi:10.1117/12.186060

9 September 1994 Analysis and modeling of submicron drain-offset polysilicon thin film transistors (TFTs)

John Damiano Jr., Le-Tien Jung, Sanjay K. Banerjee, S. Batra, M. Manning, C. Dennison

Proceedings Volume 2335, Microelectronics Technology and Process Integration; (1994) https://doi.org/10.1117/12.186060
Event: Microelectronic Manufacturing, 1994, Austin, TX, United States

Abstract

Drain-offset polysilicon thin-film transistors (DO-TFTs) with different offset lengths and doping were fabricated and characterized. The grain boundary trap states in the offset region strongly influence the electrical behavior of the TFTs. The on state current is influenced by the grain microstructure in the drain-offset region and channel region, as evidenced by the drain current activation energy measurements. The off state leakage current is dominated by the generation of carriers in the drain offset depletion region, where the trap states serve as generation/recombination centers and reduce the barrier for tunneling. A model based on the Poole-Frenkel effect and thermionic field emission was developed to account for the leakage mechanism.

Citation Download Citation

John Damiano Jr., Le-Tien Jung, Sanjay K. Banerjee, S. Batra, M. Manning, and C. Dennison "Analysis and modeling of submicron drain-offset polysilicon thin film transistors (TFTs)", Proc. SPIE 2335, Microelectronics Technology and Process Integration, (9 September 1994); https://doi.org/10.1117/12.186060

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