Simulation benchmarking for the whole resist process

Sang-Kon Kim; Ji-Eun Lee; Seung-Wook Park; Ji-Yong Yoo; Hye-keun Oh

doi:10.1117/12.536210

29 April 2004 Simulation benchmarking for the whole resist process

Sang-Kon Kim, Ji-Eun Lee, Seung-Wook Park, Ji-Yong Yoo, Hye-keun Oh

Proceedings Volume 5378, Data Analysis and Modeling for Process Control; (2004) https://doi.org/10.1117/12.536210
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

A full lithography simulation has become an essential factor for semiconductor manufacturing. We have been researching all kinds of problems for lithography process by creating and using our own simulation tool, which has contributed to extracting parameters related to exposure, post exposure bake, and development. Also, its performance has been proved in comparison with other simulation tools. In this paper, our lithography simulator and some of its features are introduced. For its benchmark, we describe our own simulator’s performance and accuracy for whole resist process by the comparison of a commercial tool. The sensitivity of process parameters and process latitude due to its parameters are discussed.

Citation Download Citation

Sang-Kon Kim, Ji-Eun Lee, Seung-Wook Park, Ji-Yong Yoo, and Hye-keun Oh "Simulation benchmarking for the whole resist process", Proc. SPIE 5378, Data Analysis and Modeling for Process Control, (29 April 2004); https://doi.org/10.1117/12.536210

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