Temperature effects on circuit synchronism

Sebastian A. Bota; Josep L. Rossello; Marcos Rosales; Jaume Segura

doi:10.1117/12.608798

30 June 2005 Temperature effects on circuit synchronism

Sebastian A. Bota, Josep L. Rossello, Marcos Rosales, Jaume Segura

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608798
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

The performance increase of VLSI circuits is leading to increase power dissipation and operation temperature, consequently management of thermally related issues is rapidly becoming one of the most challenging efforts in high performance IC design. Within die temperature gradients on silicon can occur due to different activity maps and in high performance ICs differences as high as 50 °C can be achieved during normal operation. Clock network constitutes one of the most critical elements in synchronous circuits and has a significant impact on speed, area and power dissipation. Due to the well-known impact of temperature on delay, the effect of non-uniform thermal maps on the clock skew can acquire a significant relevance. In this work we analyze the impact of within die thermal gradients on the clock skew considering the dependence on temperature on both active devices and interconnects.

Citation Download Citation

Sebastian A. Bota, Josep L. Rossello, Marcos Rosales, and Jaume Segura "Temperature effects on circuit synchronism", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608798

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