Silicon IP reuse standards for design for manufacturability

Juan Antonio Carballo; Savithri Sundareswaran

doi:10.1117/12.659829

14 March 2006 Silicon IP reuse standards for design for manufacturability

Juan Antonio Carballo, Savithri Sundareswaran

Proceedings Volume 6156, Design and Process Integration for Microelectronic Manufacturing IV; 615606 (2006) https://doi.org/10.1117/12.659829
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

Design for Manufacturability (DFM) has become a major semiconductor topic that spans various issues, including issues related to lithography hardware limitations, and issues related to variability. There is, however, an issue that crosses multiple DFM domains: the need to reuse designed Silicon IP blocks or "cores" across various manufacturing processes. Unfortunately, there are no standards to facilitate the reuse of circuit blocks while addressing the lithography- and variability-related issues. Specifically, there is no clear definition for a user of a core to evaluate "manufacturability" of a core for a set of foundry processes. We present a quantitative DFM standard for Silicon IP reuse, which addresses this problem. This work was done in conjunction with VSIA's DFM team.

Citation Download Citation

Juan Antonio Carballo and Savithri Sundareswaran "Silicon IP reuse standards for design for manufacturability", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 615606 (14 March 2006); https://doi.org/10.1117/12.659829

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