This PDF file contains the front matter associated with SPIE Proceedings Volume 12956, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

The multi-beam mask writer MBM-3000 is launched in 2023 for next generation EUV mask production. It is equipped with 12-nm beamlets and a powerful cathode that brings out a beam current density of 3.6A/cm², in order to achieve higher resolution and faster writing speed than our current writer MBM-2000PLUS. New optics with a next-generation blanking aperture array (BAA) is installed in order to double the beam count. The optics is designed to reduce the Coulomb interaction effects. It is equipped with aberration correctors to reduce image field distortion and other types of aberrations to obtain the best beam performance. Data path is enhanced by the more computation resource and a new data format MBF2.1 which supports curve representation to process curvilinear pattern data efficiently. Writing tests confirmed that the MBM-3000, which uses a 1.5X larger beam current than the MBM-2000, simultaneously enhances both resolution and throughput.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15 to 20% of the minimum half pitch. For 14nm, this means 2.1 to 2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL, an attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. To establish a new lithographic production solution requires the support of an ecosystem in order to enable seamless insertion of the technology. In this paper, review the current performance of Canon’s and then move on to discuss a variety of ecosystem technologies including drop pattern generation, NIL process simulation, virtual metrology support and pattern transfer techniques that can be applied to different markets. Finally, we touch on other applications that can be addressed with NIL and show some processing examples.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In 2018, Hiura et al. reported a mix and match overlay (MMO) of 3.4nm and a single machine overlay (SMO) across the wafer was 2.5nm using an FPA-1200 NZ2C four station cluster tool. These results were achieved by combining a magnification actuator system with a High Order Distortion Correction (HODC) system, thereby enabling correction of high order distortion terms up to K30. Unlike other lithographic methods, NIL provides the pattern flexibility and a cost structure to address a much larger application space. Potential market expansion and includes high end semiconductor devices, CMOS image sensors, optical couplers for augmented reality headsets and meta optical elements (MOEs). The purpose of this paper is to describe the patterning and pattern transfer performance enhancements to enable improved edge placement error for DRAM applications, allow the patterning of dual damascene back end structures with a simpler single step imprint patterning process and to create working MOEs operational in the visible spectrum.

As next-generation packaging substrates, the use of glass materials with low dielectric-loss characteristics is a promising approach. However, producing micro-vias in glass is still challenging because it is a brittle material that is susceptible to breaking. One potential method for fabricating high-quality holes with high aspect ratios is ablation using a high-power KrF excimer laser. In this process, the glass surface is irradiated by a high-fluence laser beam formed using a focusing lens. To produce a small-diameter focused laser beam, a low beam quality factor (M²) of close to unity is required. However, this is generally only possible for an ideal single-mode Gaussian beam. For an excimer laser beam, the M² value is larger due to the fact that the beam is produced by multi- mode oscillation. In the present study, we used a cylindrical off-axis unstable resonator with a KrF laser and obtained a high-quality beam (M²: V:7.1, H:5.4) with a high output power (58.4 mJ/pulse). With this light source, it is a feasible approach to fabricate fine holes by laser ablation with a diffraction-limited focused diameter of 20μm when an imaging lens with a focal length of 100mm was used. The laser output power was found to be similar to that for a conventional stable resonator. Gigaphoton demonstrates that a combination of a KrF excimer laser and an unstable resonator provides high-productivity fabrication of fine micro-via holes for the High-performance Advanced packaging.

A new application in the semiconductor industry that received quite some traction the past few years is bringing the transistor power delivery network to the backside of the wafer. The big gain of this change is that it frees up real estate on the frontside of the wafer, enabling a further increase of the transistor density. This so-called Back-Side Power Delivery Network (BS-PDN) application is quite challenging since it requires a direct wafer-to-wafer bonding process module. To get access to the transistor from the backside, a device wafer needs to be flipped and bonded to a carrier wafer followed by an annealing step. After these processing steps, the original substrate of the device wafer is removed by grinding and etch steps. This will enable access to the transistors from the backside of the wafer. The wafer processing continues by conventional layer deposition, lithography and etch steps, this time on the flipped wafer. Unfortunately, the bonding process module that includes the actual direct wafer-to-wafer bonding step itself, will also introduce a distortion in the device layer that has been transferred to the carrier wafer. Since the on-product overlay requirement for the first exposed layer on the backside to one of the front-side layers is tight (<10-nm today and <<5-nm in the foreseeable future), a deep understanding of the origin of the distortion fingerprint after bonding is required. In our previous work, we presented a method to isolate the distortion fingerprint due to bonding from the remaining other overlay contributors. The fingerprint we observed after linear corrections had a typical magnitude ranging from 50 to 80-nm. A clear 4-fold symmetry was observed that could be attributed to the crystal orientation of the (100) silicon substrate. We demonstrated that the scanner wafer alignment model is very capable of correcting the global 4-fold wafer distortion fingerprint. Residual levels of less than ~15-nm were shown. These residuals could be further reduced by applying a correction per exposure (CPE) recipe. We showed that performance levels of less than ~6-nm (99.7%) and ~10-nm (max) could be achieved after a 33-parameter per exposure field self-correction. The resulting wafer plots nicely revealed how to improve the overlay performance further. An increased level of residuals was found in the wafer center and at the wafer edge. In the current paper, we build upon our previous work and continue the investigation on the remaining overlay contributors that were identified previously. This time, the focus will be on the local wafer deformations that are visible after the direct wafer-to-wafer bonding step. By local we mean the distortions that manifest themselves over a very short spatial range. These local distortions cannot easily be corrected by the scanner and are typically present close to the wafer center and the wafer edge. We know that the local wafer deformation close to the wafer center is caused by the bonding pin that initiates the bond wave. To characterize the center distortion signature, we varied many experimental parameters to see the impact. We will show the impact of the die layout, the rotation of the top wafer by a 45-degrees, wafer surface properties, and substrate choice of the carrier wafer. The latter is interesting, we evaluated both (100) and (111) carrier wafers. Although the prime focus will be to improve the overlay performance on the center of the wafer, we monitor the impact of the experimental settings on the wafer edge and remaining part of the wafer as well. We present a path forward to mitigate the local distortions such that they will not be blocking for high volume production.

The use of imprint resists in the frame of a multi-layer systems is a viable and also very effective approach to overcome critical challenges typically associated with the patterning and fabrication of demanding nano-patterned substrates like high-aspect ratio structures often applied e.g. in optical devices. The high etch performance of the systems needed for such pattern transfers is either realized by the fabrication of in situ etch masks or by the preparation of a metal hard mask after the imprint and subsequent etch processes. While it might seem counterintuitive at first glance, to split the different features and functions of one resist into different materials and layers, the overall fabrication process however becomes more inherent robust and is moreover also easier adaptable to changes and modifications like e.g. the use of other substrate materials). Herein, we present in detail different types of multi-layer material systems that are all realized by applying candidates of the mr-NIL210 resist series.

This manuscript investigates the use of Nanoimprint Lithography (NIL) for the development of devices in semiconductor, photonic, and biomedical industries. It focuses on the SmartNIL^® process, a method for patterning nanostructures on various materials. The study highlights the advantages of NIL, such as mass production of micro- and nano-scale structures, and the replication of complex structures. The manuscript discusses the importance of a precisely controlled and uniform residual layer for optimizing the optical performance of photonic components. It compares conventional spin coating with inkjet coating, emphasizing the latter’s superior material efficiency and compatibility with the SmartNIL^® process. Two different resins were investigated: a nano-filler free material, EVG UV/A NIL (n=1.5), and a high refractive index resin containing TiO2 nanoparticles from INKRON (n=1.9). The results for both resins demonstrated excellent pattern fidelity with sharp edges and no filling issues across the entire imprint. The EVG UV/A NIL resin showed a uniform residual layer ranging from 30 to 40nm across the entire area, with the structure height gradually increasing from 80 to 275nm. The INKRON resin displayed a progressive increase in structure height from 68nm to 305 nm, with the thickness of the residual layer varying between 44 and 60nm. The results demonstrate the achievement of a uniform residual layer over a progressive height increasing pattern.

Eliminating the need for multilayer alignment in nanoscale manufactured devices will streamline the lithography process and open up avenues for flexible substrate roll-to-roll (R2R) manufacturing. A system capable of single-exposure 3D holographic lithography with in-line metrology and real-time feedback will revolutionize micro and nano manufacturing. Work towards such developments are demonstrated to show promise in the field of nanopatterning.

Laser direct write lithography using near-i-line wavelength is a very fast, versatile, and cost-effective maskless technique for fabricating microstructures, especially for prototyping and low-volume production in many fields of application, e.g. microelectronics, photonics, optical devices, and mastering. However, the resolution of this method is limited and depends on the focal length of the write lens used, which means that it is necessary to find a tradeoff between write speed and resolution. In this paper, we will optimize the resolution of i-line direct write processes by applying resolution enhancement techniques, which are well known in stepper lithography. IMS Chips and Heidelberg Instruments collaborated on tuning both process and tool performance with the goal to improve structure density and resolution.

High–volume–capable Maskless Exposure technology is demonstrated to deliver fast and individualized production abilities for micro-optical applications, individual device labelling and micro–structuring of novel RGB–colored photoresists at the die level. Dynamic alignment enables real–time distortion compensation and adaptive repositioning of sub 2μm structures during write–time enabling novel possibilities for heterogenous integration and associated applications.

Hydrogen Depassivation Lithography has become established as the method for atomic-precision patterning for 2D dopant-based devices, such as qubits and analog quantum simulators. Research thus far in this area has mostly been focused on patterning of n-type dopants, such as P and As. In this work, we describe the process for fabrication of bipolar dopant-based devices, such as p-n junctions and n-p-n bipolar junction transistors, which may have a number of advantages such as improved gain-bandwidth product and low-noise operation. The P-doped parts of the device are created first, and the B-doped parts are created subsequently, requiring atomically-precise alignment to the P-doped parts. To achieve the necessary patterning precision, we have developed various advances to conventional STMs, including corrections for piezo creep and hysteresis, automatic lattice alignment, and spectroscopic imaging methods to give strong contrast of surface and buried dopants. The overall process described here has become known as Atomically Precise Advanced Manufacturing (APAM), which offers far better patterning precision than conventional techniques such as e-beam lithography.

For two decades, the Technische Universität Ilmenau has been developing high precision Nanopositioning and Nanomeasuring machines (NPMMs). These have proven their potential for nanometer accurate measurements in large volumes up to 200mm x 200mm x 25mm with 5 axis operation in several fields. As these machines operate according to the highest standards of metrology, offer picometer resolution and nanometer uncertainty, the goal is to transfer their unique precision to fabrication and patterning. So far, the NPMMs have been equipped with laser-based as well as tip-based patterning tools, including one photon and two photon polymerization, nanoimprint, scanning probe lithography and combinations of these technologies. The goal is basic research on these technologies, to tackle the evident challenges and explore the concealed limits to estimate the potential for later use in an industrial scale. In this paper, the specifics and advantages of the NPMMs will be described as well as the micro- and nanofabrication tools that are currently worked on. Focus is on the parameters in measurement mode and the accomplished fabrication results.

Block copolymers (BCP) self-assemble into a variety of microstructures and controlling the orientation of these structures relative to the substrate surface allows for their use in lithographic techniques. Control over the orientation is non-trivial and requires chemical treatment of the substrate or external fields that can interact and orient these BCP microstructure domains. With this research we highlight a facile thin film casting methodology that produces and orients diblock copolymer microstructure perpendicular to the substrate in the casting process itself. The films are cast from a solvent mixture with a block selective Ionic Liquid (IL) that plasticizes the BCP, enhances repulsive interactions between blocks, and screens preferential interactions between the BCP and the substrate. With a well-developed and fully perpendicular microstructure these films can find applications in sub-20nm lithography processes and as ultrafiltration membranes after selectively etching out the assembled domains.

The evolution of the photolithographic model has enabled the semiconductor industry to achieve enhanced device efficiency within the consumer electronics domain through the ability to create diminutive shapes and sizes. This historical progression can be delineated into six discernible periods, all of which are based on fundamental elements of a light source and a lens: broadband, i-line, KrF (248nm), dry ArF (193nm), immersion (193nm), and the present environment belonging to the dynamic and evolving Extreme Ultraviolet (EUV) generation (13.5nm). Accompanied by this evolution, three supplementary patterning modalities have synergistically evolved to augment and extend the capacities of the lithographic approaches: Reactive Ion Etching (RIE), Chemical Mechanical Planarization (CMP) and Atomic Layer Deposition (ALD). The current EUV generation presents unique scaling challenges such as overlay discrepancies, critical dimension (CD) variance, and EUV exposure capacity limitations. To mitigate these scaling impediments and continue the miniaturization trajectory, Directed Self-Assembly (DSA) represents the nascent fourth era of complimentary patterning. DSA has the potential to tackle the foremost triad of scaling challenges pervading the contemporary industry landscape. In this discourse, we shall explain the profound role of DSA in the future of semiconductor fabrication. Specifically, we will critically assess the readiness to produce DSA materials and their potential for continued extension beyond the existing PS-b-PMMA generation platform.

Continuous scaling by extreme ultraviolet (EUV) lithography is tightening the patterning requirements for photoresist materials. Specifically, chemically amplified resists (CAR) are facing significant challenges to keep supporting the patterning needs. In view of this, complementing EUV lithography with directed self-assembly (DSA) of block copolymers offers interesting opportunities to enable the use of CAR towards ultimate resolution. As DSA decouples the resist patterning performance from the final pattern quality, roughness and defects in the resist pattern can be rectified. Here, we discuss the impact of material and process parameters on the rectification performance by DSA, both for line-space and hexagonal contact hole arrays.

Greyscale lithography is applied to manufacture complex 2.5D and freeform microstructures in photoresists which serve as master for the pattern transfer into materials for permanent applications, often used in micro-optics. We present the results and the challenges in reproducible generation of deep greyscale patterns in a highly sensitive greyscale positive photoresist, mr-P 22G_XP, when using photomask-based mask aligner greyscale lithography in contrast to laser direct writing on which resist development had been focused. Furthermore, we show the influence of resist aging on the resist response, and ways to correct it by process adaption, as well as we conclude requirements to greyscale photomasks suitable to make use of the full potential of the mr-P 22G_XP resist dedicated for >100μm deep greyscale patterns.

Field-effect transistors (FETs) with channels of two-dimensional transition metal dichalcogenides (2D TMDs) are expected to extend Moore’s law by extreme scaling of contacted gate pitch (CGP) post silicon-sheet-based complementary FET (CFET) devices. The ultrathin body and fully passivated surface of 2D materials result in superior electrostatic control and improved short channel behavior. Challenges such as high contact resistance or lack of doping technology are on the way of 2D-FETs reaching the required performance for high-performance logic applications. Additionally, in order to integrate 2D TMDs in ultra-scaled CMOS devices, developing a patterning scheme via the state-of-the-art extreme ultraviolet (EUV) lithography is essential. In this paper we demonstrate our first results on studying the compatibility and interaction of semiconducting 2D TMDs with EUV environment using a set of characterization techniques that are fit to detect qualitative defects and morphological changes in these atomically thin layers. Our study is focused on semiconducting TMDs that are currently the most promising candidates for transistor channels: MoS₂ (NMOS) and WSe₂ (PMOS). We report the interaction of EUV photons and photo-electrons with blanket films of MoS₂ and WSe₂ for different EUV doses in vacuum environment. Based on the current findings we propose design of experiments aiming at developing controllable and tunable modification and patterning of 2D TMDs with the EUV energy and resolution for advanced device nodes.

In this paper, a patterning approach via i-line grayscale exposure is presented. The i-line wafer stepper (NIKON NSR2205i11D) together with specialized grayscale reticles from Benchmark Technologies (USA), manufactured with half-toning technique, are used. The positive tone and low contrast grayscale ma-P 1275G photoresist is manufactured by Micro Resist Technology (Berlin, Germany) and used in this work; it is part of the ma-P 1200G grayscale resist series and can cover a thickness range of 5 μm to 14 μm. The lithographical pattering process is performed on 6-inch wafers. Essential parameters like the contrast curve measured in the resist as well as after the dry etching are evaluated. Different 2.5D structures like micro lens arrays, blazed gratings, frustums and Fresnel lenses are fabricated by i-line stepper gray scale lithography and ma-P 1275G demonstrating its excellent behavior to generate 2.5D grayscale patterns. For the characterization of the generated 2.5D grayscale patterns a stylus profilometer, atomic force microscopy (AFM), scanning electron microscopy (SEM) and confocal microscope are used. In this paper the process of setting up a grayscale exposure with an i-line stepper and a grayscale reticle and the need to adapt the grayscale reticle in different iterations is presented and discussed.

Hierarchical structures that combine microlens arrays and nanostructures exhibit exceptional potential in enhancing optical characteristics of optoelectronic devices. Furthermore, multi-scale architectures confer multifunctional capabilities to these devices. Existing methodologies for creating hierarchical structures can be classified by the initial structure fabricated: the "microfirst" and "nanofirst" approaches. Among these, the nanofirst strategy stands out as the most versatile, despite presenting challenges in 3D micropatterning on existing nanostructured surfaces. However, it leads to a greater challenge involving 3D micropatterning on existing nanostructured surfaces. To address this challenge, we propose a novel technique for fabricating hierarchical 3D microstructures through controlled bending of suspended microdisks. This method offers new perspectives on achieving hierarchical structures and 3D microstructures.

3D patterns and miniaturization have emerged as key paths for novel applications in microelectronics, optics, photonics and more. However, the current manufacturing techniques for high-resolution 3D patterning are complex, slow, and expensive. Here, we combine grayscale electron-beam lithography (g-EBL) and nanoimprint lithography (NIL) to overcome these challenges. Indeed, g-EBL allows the fabrication of complex structures with high resolution, while NIL can replicate complex patterns down to the nanometer scale with reduced time and cost. In a first step, the master is fabricated by grayscale electron beam lithography to obtain high resolution. This "resist master" is employed to prevent possible pattern deformation caused by etching and stripping steps. In a second step, this master is replicated by NIL to increase the throughput. In addition, different characterizations are performed after each step in order to evaluate the process. The morphology, dimensions and material properties are studied.

Adaptive Optics (AO) systems add value in applications that involve light collection through turbulent media. Examples include Earth-based telescopes, microscopy, optical communication, and high-energy lasers, where solutions for addressing distorted images are needed. A key challenge in building AO systems involves achieving sufficient correction of distorted images through optical elements that can change shape with enough vertical displacement, spatial resolution, and frequency to adequately correct images. One such AO element is a deformable mirror that is bonded to an array of MEMs-based actuators that is made to operate using the Lorentz force. These elements can operate with very low power and are known as Low-Voltage Deformable Mirrors (LVDM). This study delves into a multi-step Potassium Hydroxide (KOH) etching process, encompassing surface preparation, mask deposition, lithography, and etching. KOH bulk micromachining proves critical in precision crafting of detailed 3D microstructures through anisotropic wet etching, offering unparalleled control over structural depth and morphology. LVDM Lorentz actuators are systematically arrayed in 20 × 20 geometries, interconnected with a flexible, reflective membrane mirror. Fabrication of the actuator arrays using Silicon on Insulator (SOI) wafers utilizes a multi-step KOH bulk process, with a design that integrates a crossbar, pillar, and springs, with a need for a crucial depth of up to 35μm. This study provides a detailed account of the two-step KOH etching process, emphasizing critical parameters for successful Lorentz actuator fabrication on SOI wafers. Exploration of process variables like temperature, etchant concentration, and etching time is undertaken, considering their impact on etch rate and selectivity. Understanding these variables proves vital for achieving high-quality and reproducible MEMS structures in micro-/nanofabrication. The study also tackles challenges associated with multistage anisotropic wet etching, including etch pit formation, crystallographic defects, and surface roughness. Strategies to mitigate these challenges, such as surfactant use, additives, and post-etch treatments, are discussed, emphasizing their effectiveness in improving final device performance and reliability.

Integrated photonics offer a miniaturization potential for applications like sensing, data communication, as well as emerging quantum technologies. In this paper we show optical loss measurements for different e-beam approximation, data preparation, and exposure strategies concerning optical waveguides. The focus is on both, the decrease of e-beam writing time and the reduction of optical loss, which is achieved by applying Vistec’s shot count optimized and edge roughness aware JES Approximation, as compared to the common Border Approximation.

In this paper, a general review of the past progress, current status and future perspective of MEMS/NEMS based maskless EUV digital lithography for high-resolution semiconductor manufacturing is presented. Starting from the maskless patterning resolution and throughput requirements, we shall discuss the unique characteristics of digital EUV lithography spanning from optical and system-level design, imaging methodology, writing engine, to device process development and fabrication progress achieved. The wafer scan induced image blur impacts maskless writing speed and imaging strategy. The required high demagnification and redundant multiple-pulse exposure help to enable the defect-tolerant printing. Digital EUV lithography allows multiple/sequential stitching exposures in one scanning process without throughput penalty, thus can simplify the patterning process and amplify its competitiveness in high- NA application. Moreover, its grayscale/analog imaging principle not only significantly reduces the data rate but also provides an efficient way to enhance the resolution capability. Dynamics, control and design of electrically damped MEMS/NEMS devices will be examined. A low-temperature LPCVD SiGe process for MEMS/IC integration has been developed and the micromirror fabrication results will be reviewed. It is shown that reflective nanomirrors based maskless approach is one path to cost-effective and defect-tolerant compact EUV lithography, which helps to create emerging opportunities for low-volume but cutting-edge IC applications. Potential processing challenges and scaling issues of nanomirror device technology for a timely insertion of digital EUV lithography into future advanced IC manufacturing will also be discussed.

Stems from the challenge to manufacture advanced semiconductor devices with a Critical Dimension (CD) of 100 nm or even 90 nm, the resolution enhancement lithography assisted by chemical shrink (RELACS) is proposed to increase the resolution of the i-line or KrF lithography. RELACS technology gets rid of the dependence on expensive ArF lithography equipment at 150-90 nm process nodes, and continuously reduces the two-dimensional size of the pattern on the wafer through the interfacial chemical reaction between the shrink materials and the photoresists. Meanwhile, good control of the line edge roughness (LER) after the interface chemical reaction is important for semiconductor mass production, and Hitachi's CD-SEM (CS4800) instrument provides roughness (LER/LWR) measurement technology. RELACS technology offers a new possibility for the development of advanced processes in the semiconductor manufacturing.

We report on a new developed interference lithography system that allows flexible design of the slant angle and pattern pitch of the diffraction grating. The system consists of two optical paths moving on an arc stage and another stage moving horizontally with precision, allowing the slant angle and pattern pitch to be controlled up to ±25 degrees and from 150 to 500nm, typically. In addition, this system is equipped with a fine stage for semiconductor lithography, diode-pumped solid-state lasers with wavelengths of 266nm and 355nm, and a high-resolution actuator to achieve 0.01nm pitch accuracy and high contrast exposure. Slant gratings with different angles and directions depending on their position on a wafer can be processed with this system. This presentation will also introduce various structures developed with this system and examples of their potential applications.

Hybrid polymers are a class of materials especially suited for micro-optical applications due to their outstanding transmission and excellent stability towards temperature, chemicals and radiation. They are solvent-free viscous liquid and therefore UV-replication has become the most established process for their usage in micro-optics manufacture. However, they have also comparable processing behavior to classical photoresists and can be processed in versatile ways offering further possibilities for 2D and 3D structuring. Herein, we report on different UV-lithographical technologies to create high-aspect and high resolution pattern with hybrid polymers.

Multibeam Corporation is redefining electron beam lithography with its groundbreaking Multicolumn Electron Beam Lithography (MEBL) systems. These fully automated tools utilize an array of miniaturized electron columns and sophisticated algorithms to achieve high-speed, high-resolution patterning across the entire wafer. This innovative maskless technology enables extraordinary design flexibility, accelerating learning cycles and speeding time to market for advanced chip designs. MEBL's high throughput and adaptability empower foundries to rapidly explore new ideas, making possible a new generation of customized semiconductor products. Designed with the capability to complement and bolster photolithography processes, this maskless manufacturing approach further accelerates time to market and significantly reduces costs, particularly for low-volume, high-mix production.

Microlithography has traditionally involved a photoinduced solubility change, necessitating a solvent development step. Self-developing resists, in which photolysis results in volatile products, were pioneered in the 1980s but they failed to find commercial traction due in part to fear of contaminating expensive high-resolution projection optics. We have adapted similar chemistry for three applications: high-throughput placement of very large arrays of entire components, such as semiconductor chiplets and microLEDs; direct-write photolithography with thermal development; and a nanoscale-resolution lithography tool based on a modified AFM tip with controlled heating. In the first system, decomposition to small gaseous molecules in a short (of the order of microseconds) time propels the component onto a target substrate. Lithography requires in particular high contrast and stable post-development features. For the third case, decomposition must be endothermic, devoid of residue upon the application of heat, and responsive to both pressure and temperature. Promising results have been obtained for each.

In this work, Zeon introduces the resolution with ZEP530A without PFAS restriction for dense L/S, iso-space and iso-line patterns on Si wafer by F7000S with VSB type in EB drawing equipment. Zeon examined litho-performance at dense L/S in changing 3 kinds of developers. The new developer of ZED-K90 (R&D sample) with lower both viscosity and solubility enabled to get lower roughness and enhance the resolution than those of ZED-N60 and N70 on LER although the dose to size was getting higher. There were some pinching defects on the patterns by ZED-N60 due to too strong solubility. On the other hand, ZED-N70 and K90 can be less on them due to the appropriate solubility. Next, litho-performance with ZEDK90 at iso-space and iso-line patterns was evaluated. The resolution was at design CD18nm in iso-line pattern and at design CD12nm in iso-space pattern and it was the best resolution among 3 developers. Additionally, the LER and SER with ZED-90 got lower than those with ZED-N70. It was clarified that the combination of ZEP530A and ZED-N90 had the sufficient potential to both enhance litho-performance including the resolution in EB resists and utilize them for EUV mask.

Nanoimprint lithography (NIL) is regarded as a promising technique for application to fabrication of the dual damascene structures that are commonly fabricated in back-end-of-line layers. Initial development work has commenced with a simple single-level process to evaluate the suitability of NIL for back-end processing applications. In this work, a test pattern with a minimum half-pitch of 24nm was patterned using NIL, and W damascene interconnects were then fabricated via a combination of W deposition followed by chemical mechanical polishing. The electrical performances of the test devices were subsequently evaluated using the open/short test element group. The line resistances and leakage currents of the W interconnect structures fabricated using NIL showed good cumulative distributions at the designed minimum linewidth of 24nm. We also demonstrated that a diagonal zigzag capacitor pattern with a pattern size of 2X nm showed good electrical properties.

Curvilinear shapes are created by ILT (Inverse Lithography Technology) from design layouts, to compensate lithography process errors. Such shapes are better stored as combination of polygons and curves than merely polygons for efficiency reasons as modeling runtime, mask-writing time, and data volume. This is why a curvilinear format has been proposed by mask-writer suppliers, while its OASIS counterpart has been developed by a curvilinear work group created in 2019. As for their curve parts, these curvilinear formats support: Explicit Bézier, B-Spline, and Implicit Bézier curves. The last two are of particular interest, since they both offer more compaction properties than Explicit Bézier curves, from which they are derived. This paper introduces the different curves as mathematical objects in order to derive their properties, advantages, and disadvantages in terms of compaction and conversion capabilities.

This paper introduces a new AI-enpowered method for accurately measuring submicron structures with high aspect ratios (HAR) in semiconductor packaging using spectral scatterometry across DUV, visible, and SWIR wavelengths. By optimizing polarization and spectrometer calibration, the method improves spectral signal contrast for precise critical dimension (CD) metrology. An Artificial Neural Network (ANN) tackles phase shift problems for trench spacings near light wavelengths, enabling precise CD measurement. Experiments demonstrate DUV light's proficiency in measuring small CD differences and VIS and SWIR's effectiveness for larger, deeper structures. The DUV system measures HARs up to 10:1 and apertures down to 0.46 μm with accuracy within 3% of Focused Ion Beam/Scanning Electron Microscope (FIB/SEM) comparisons.