Domain specific architectures, hardware acceleration for machine/deep learning

Angel I. Solis; Patrica Nava

doi:10.1117/12.2519554

10 May 2019 Domain specific architectures, hardware acceleration for machine/deep learning

Angel I. Solis, Patrica Nava

Proceedings Volume 11013, Disruptive Technologies in Information Sciences II; 1101307 (2019) https://doi.org/10.1117/12.2519554
Event: SPIE Defense + Commercial Sensing, 2019, Baltimore, MD, United States

Abstract

This article aims to provide the reader with a clear understanding of a subdiscipline in artificial intelligence, Deep Neural Networks. In addition to this, we cover a set of proposed Domain Specific Architectures, Accelerators, that are optimized for these types of computations. In optimizing these computations, we are able to reduce data transfers by keeping data at the processing unit in their individual register files thus increasing energy efficiency per computation.

Conference Presentation

Citation Download Citation

Angel I. Solis and Patrica Nava "Domain specific architectures, hardware acceleration for machine/deep learning", Proc. SPIE 11013, Disruptive Technologies in Information Sciences II, 1101307 (10 May 2019); https://doi.org/10.1117/12.2519554

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