Continuous shrinking of semiconductor manufacturing node requires smaller critical dimension (CD) and higher pattern density, but also a better control of pattern local variability such as local CD uniformity (CDU). Thus, improving the process stability has been shown to improve local variability. Shrinking makes also crucial to control the process-specific patterned defectivity, with a more demanding defect detection and removal effort, which will depend on the mask level and stack materials. Therefore, integrating a new process in a recently installed immersion lithography cluster requires a thorough study of the influence of the track parameters in the specific process flow, as well as the use of last generation optical defectivity inspection, review and classification tools. In this work, we present the main results in the cooptimization of CD control, CD uniformity and after development inspection (ADI) of defectivity in a PTD immersion lithography process. The mask used is a gate layer targeting 42nm dense lines using a trilayer with topcoat lithographic stack.
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