Exploiting wafer level packaging of VCSELs on silicon photonic integrated circuits (PICs) with the advantages of a novel, flip-chip bonding, active dry-alignments method on SOI up-reflecting mirrors (Conference Presentation)

Giovanni Delrosso

doi:10.1117/12.2633800

11 October 2022 Exploiting wafer level packaging of VCSELs on silicon photonic integrated circuits (PICs) with the advantages of a novel, flip-chip bonding, active dry-alignments method on SOI up-reflecting mirrors (Conference Presentation)

Giovanni Delrosso

Author Affiliations +

Proceedings Volume 12222, Optical System Alignment, Tolerancing, and Verification XIV; 122220E (2022) https://doi.org/10.1117/12.2633800
Event: SPIE Optical Engineering + Applications, 2022, San Diego, California, United States

Abstract

In this paper, we describe a successful method to power-on VCSELs while performing active dry-alignment with optical coupling structures on PICs. Dry-alignment is here intended as an optical coupling approach with no temporary or permanent bonding of coupled parts together. Emphasis has been done on achieved results showing low insertion losses (typ. <3dB) obtained when coupling single-mode 1.55um InP VCSEL light beams on top of up-reflecting mirrors (URMs) realized with VTT 3um SOI Silicon Photonic (SiPh) platform. The described method demonstrates a dramatic coupling efficiency increment, overwhelming de-facto most of the drawbacks of the current industry-standard approach when using passive alignments. VCSELs can be tested and replaced several times without any visible damage. A limiting factor such as off-axis errors in VCSELs when coupled with URMs, will be greatly compensated with active dry-alignment. VCSELs´ assembly time on PIC is expected to be 3-5 times longer than with the passive alignment.

Conference Presentation

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Giovanni Delrosso "Exploiting wafer level packaging of VCSELs on silicon photonic integrated circuits (PICs) with the advantages of a novel, flip-chip bonding, active dry-alignments method on SOI up-reflecting mirrors (Conference Presentation)", Proc. SPIE 12222, Optical System Alignment, Tolerancing, and Verification XIV, 122220E (11 October 2022); https://doi.org/10.1117/12.2633800

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KEYWORDS

Vertical cavity surface emitting lasers

Photonic integrated circuits

Semiconducting wafers

Silicon photonics

Integrated circuits

Mirrors

Wafer bonding

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