2D local interconnect metal patterning exploration for CFET

Hsinlan Chang; Youssef Drissi; Gioele Mirabelli; Odysseas Zografos; Yasser Sherazi; Julien Ryckaert; Gaspard Hiblot

doi:10.1117/12.3010804

10 April 2024 2D local interconnect metal patterning exploration for CFET

Hsinlan Chang, Youssef Drissi, Gioele Mirabelli, Odysseas Zografos, Yasser Sherazi, Julien Ryckaert, Gaspard Hiblot

Proceedings Volume 12953, Optical and EUV Nanolithography XXXVII; 129530Y (2024) https://doi.org/10.1117/12.3010804
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States

Abstract

To keep up with the pace set by Moore's law, an innovative standard cell architecture called CFET has been proposed recently. Its technical challenge is to stack transistors on top of each other to achieve higher density. Nevertheless, the targeted nodes still require very small dimensions in terms of pitches, critical dimensions (CD) and tip-to-tip, but also in terms of geometries. In this paper we explore the patterning of a 2D local interconnect, Middle of the Line (MOL) layer with aggressive pitches and spaces that has been foreseen as a possible option for this CFET architecture. Multiple patterning solutions are proposed including 1- EUV print with multiple colors, 2- Spacer assisted solutions with multiple cut patterns. Finally, we evaluate the benefit of using 3- High NA EUV lithography as a potential candidate for this type of layer.

Conference Presentation

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Hsinlan Chang, Youssef Drissi, Gioele Mirabelli, Odysseas Zografos, Yasser Sherazi, Julien Ryckaert, and Gaspard Hiblot "2D local interconnect metal patterning exploration for CFET", Proc. SPIE 12953, Optical and EUV Nanolithography XXXVII, 129530Y (10 April 2024); https://doi.org/10.1117/12.3010804

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