Assessing need and methodology for mask constraints in ILT applications

Mohamed Ramadan; Chris Progler; Henry Kamberian; Jinju Beineke; Michael Green; Guangming Xiao; Ming-Feng Shen; Kai-Hsiang Chang; Kyle Braam; Alex Zepka; Yu-Po Tang; Szu Ping Chen; Eric Huang; Gloria Yeh; Nicole Wu; Chun-Cheng Liao

doi:10.1117/12.3042434

12 November 2024 Assessing need and methodology for mask constraints in ILT applications

Mohamed Ramadan, Chris Progler, Henry Kamberian, Jinju Beineke, Michael Green, Guangming Xiao, Ming-Feng Shen, Kai-Hsiang Chang, Kyle Braam, Alex Zepka, Yu-Po Tang, Szu Ping Chen, Eric Huang, Gloria Yeh, Nicole Wu, Chun-Cheng Liao

Author Affiliations +

Proceedings Volume 13216, Photomask Technology 2024; 132161Q (2024) https://doi.org/10.1117/12.3042434
Event: SPIE Photomask Technology + EUV Lithography, 2024, Monterey, California, United States

Abstract

Through techniques such as ILT, curvilinear designs and their associated masks have demonstrated benefits over Manhattan type for delivering superior wafer lithography process latitude. Moreover, a number of native design applications such as silicon photonic IC and curvilinear interconnect require delivery of masks with non-Manhattan geometries. Consequently, as enabled by the use of multi-beam mask writers (MBMW), we see the adoption of curvilinear masks in production to grow steadily. One of the more challenging topics for curvilinear adoption is on determining the optimum tradeoff between mask manufacturability and wafer imaging. To maximize the benefits of curvilinear masks without incurring an undue impact from mask complexity, it is beneficial to develop optimized layout validation checks such as MRC which can be implemented to achieve an optimum tradeoff. We will present a methodology to perform curvilinear mask manufacturability optimization using a specially designed set of parametric curvilinear test patterns. The techniques are demonstrated in support of a DRAM implementation study where ILT is applied to improve the wafer performance of a contact type layer. We describe a parametric test chip covering curvature, width, space and area and the mask data generated is applied to evaluate different curvilinear layout constructs and correlations between mask manufacturability and simulated wafer performance. We revisit the question on whether ILT actually leads to relaxed MRC constraints compared to Manhattan designs for the same design application. In addition, advanced mask characterization techniques such as 2D contouring are applied to consider the limitations of purely geometrical rule checking versus a full model based approach that can consider mask pattern fidelity in ILT layout generation.

Conference Presentation

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

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Mohamed Ramadan, Chris Progler, Henry Kamberian, Jinju Beineke, Michael Green, Guangming Xiao, Ming-Feng Shen, Kai-Hsiang Chang, Kyle Braam, Alex Zepka, Yu-Po Tang, Szu Ping Chen, Eric Huang, Gloria Yeh, Nicole Wu, and Chun-Cheng Liao "Assessing need and methodology for mask constraints in ILT applications", Proc. SPIE 13216, Photomask Technology 2024, 132161Q (12 November 2024); https://doi.org/10.1117/12.3042434

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