CORDIC processor architectures

Johann F. Boehme; D. Timmermann; H. Hahn; Bedrich J. Hosticka

doi:10.1117/12.49829

1 December 1991 CORDIC processor architectures

Johann F. Boehme, D. Timmermann, H. Hahn, Bedrich J. Hosticka

Proceedings Volume 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II; (1991) https://doi.org/10.1117/12.49829
Event: San Diego, '91, 1991, San Diego, CA, United States

Abstract

As CORDIC algorithms receive more and more attention in elementary function evaluation and signal processing applications, the problem of their VLSI realization has attracted considerable interest. In this work we review the CORDIC fundamentals covering algorithm, architecture, and implementation issues. Various aspects of the CORDIC algorithm are investigated such as efficient scale factor compensation, redundant and non-redundant addition schemes, and convergence domain. Several CORDIC processor architectures and implementation examples are discussed.

Citation Download Citation

Johann F. Boehme, D. Timmermann, H. Hahn, and Bedrich J. Hosticka "CORDIC processor architectures", Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); https://doi.org/10.1117/12.49829

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