JPEG image compression hardware implementation with extensions for fixed-rate and compressed-image editing applications

Martin P. Boliek; James D. Allen; Tadanori Ryu; Yutaka Sato; Jun-ichi Hara

doi:10.1117/12.174954

2 May 1994 JPEG image compression hardware implementation with extensions for fixed-rate and compressed-image editing applications

Martin P. Boliek, James D. Allen, Tadanori Ryu, Yutaka Sato, Jun-ichi Hara

Author Affiliations +

Proceedings Volume 2187, Digital Video Compression on Personal Computers: Algorithms and Technologies; (1994) https://doi.org/10.1117/12.174954
Event: IS&T/SPIE 1994 International Symposium on Electronic Imaging: Science and Technology, 1994, San Jose, CA, United States

Abstract

This paper describes a new high speed image compression hardware implementation which, in addition to implementing the JPEG baseline system, can be used in fixed-rate compression systems and in systems that allow editing of compressed images. High speed (CCIR 601 resolution at 30 frames/second) and small silicon size are achieved by using a unique parameterized orthogonal transform. This implementation is compatible with the DCT, yet requires no additional multiplications. Also described here is a system that uses a dynamic quantization scalar circuit to achieve fixed-rate compression and a system that utilizes the `static coefficient DPCM' feature to compress and decompress regions of interest within an image for editing or viewing.

Citation Download Citation

Martin P. Boliek, James D. Allen, Tadanori Ryu, Yutaka Sato, and Jun-ichi Hara "JPEG image compression hardware implementation with extensions for fixed-rate and compressed-image editing applications", Proc. SPIE 2187, Digital Video Compression on Personal Computers: Algorithms and Technologies, (2 May 1994); https://doi.org/10.1117/12.174954

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