Design tips and experiences in using reconfigurable FLEX logic

Peter J. Covert

doi:10.1117/12.255809

21 October 1996 Design tips and experiences in using reconfigurable FLEX logic

Peter J. Covert

Proceedings Volume 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic; (1996) https://doi.org/10.1117/12.255809
Event: Photonics East '96, 1996, Boston, MA, United States

Abstract

As field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) become faster, denser, and cheaper, many designers that previously used programmable logic devices (PLDs) and have a need in their next design for more functionality in a smaller footprint or board space have switched to using these FPGAs or CPLDs to incorporate their design. With the advent of JTAG 1149.0 boundary test specification, a specified method for reprogramming the FPGAs and CPLDs live in the field was invented. Using the electrical-erasable manufacturing process, reconfigurable hardware or logic was invented. It is perfect for prototyping as well as field applications where upgrades can be done live in a matter of seconds from personal computers that a new redesign has just been compiled. In this paper I discuss several issues experienced while using the EPX780 reconfigurable FPGA such as (1) why the new design required a reconfigurable FPGA, (2) problems encountered in implementation including place and route, compiling, simulating, and testing, and (3) the future use of the reconfigurable hardware devices including selection of proper development systems. Overall there are several tips and design rules in using reconfigurable devices generally and FLEX 780s development specifically.

Citation Download Citation

Peter J. Covert "Design tips and experiences in using reconfigurable FLEX logic", Proc. SPIE 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (21 October 1996); https://doi.org/10.1117/12.255809

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