Design of a low-power 1.5-Gb/s CMOS 1:4 demultiplexer IC

Wencai Lu; Zhigong Wang; Lei Tian; Tingting Xie; Yi Dong; Shizhong Xie

doi:10.1117/12.444554

16 October 2001 Design of a low-power 1.5-Gb/s CMOS 1:4 demultiplexer IC

Wencai Lu, Zhigong Wang, Lei Tian, Tingting Xie, Yi Dong, Shizhong Xie

Author Affiliations +

Proceedings Volume 4603, Fiber Optics and Optoelectronics for Network Applications; (2001) https://doi.org/10.1117/12.444554
Event: International Symposium on Optoelectonics and Microelectronics, 2001, Nanjing, China

Abstract

A monolithic integrated photoreceiver for 1.55-micrometers wavelength fiber-optic receivers has been designed and fabricated with one amplifier stage, two stages of source follower and a feedback resistance structure. The optoelectronic integrated circuit (OEIC) receiver combines an InGaAs MSM photodetector with InP-based InA1As/InGaAs HEMT. The receiver demonstrates a transmitting bit rate of 2.5Gb/s with a transimpedance of 58(Omega) dB. While operating at 2.5Gbit/s, the chip consumes 160 MW at a single+5V supply voltage.

Citation Download Citation

Wencai Lu, Zhigong Wang, Lei Tian, Tingting Xie, Yi Dong, and Shizhong Xie "Design of a low-power 1.5-Gb/s CMOS 1:4 demultiplexer IC", Proc. SPIE 4603, Fiber Optics and Optoelectronics for Network Applications, (16 October 2001); https://doi.org/10.1117/12.444554

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