Paper
30 July 2002 Tandem process proximity correction method
Kohji Hashimoto, Tatsuaki Kuji, Shingo Tokutome, Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
Author Affiliations +
Abstract
Tandem process proximity correction (PPC) method is proposed for a novel PPC methodology in low k1 lithography. A features of this method is that proximity corrections for unit process (mask fabrication process, lithography process on wafers, etching process on wafers) are carried out in reverse order of process events in the mask EB data processing. Also, each correction model or rule is individually obtained with traces of experimental unit process proximity effects (PPE). An optically-related-model could be applied to only lithography PPC, for example, and optically-unrelated-models or rules could be applied to other unit PPCs. The above features indicate the possibilities of performing an accurate correction model with the large etching PPE. In addition, the tandem PPC could be available to optically-unrelated pattern shrinkage processes in low k1 lithography; those are a resist- slimming process, a thermal-flow-resist process and so on. The PPC model accuracy is discussed with the application to 0.13 um-ruled DRAM gate process and the result provides better performance. The features also imply that the tandem PPC involves the short turn-around-time (TAT) of a remodeling of an updated mask fabrication process. This is because the mask fabrication process update only requires the alternation of the mask PPC model in the tandem PPC.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kohji Hashimoto, Tatsuaki Kuji, Shingo Tokutome, Toshiya Kotani, Satoshi Tanaka, and Soichi Inoue "Tandem process proximity correction method", Proc. SPIE 4691, Optical Microlithography XV, (30 July 2002); https://doi.org/10.1117/12.474486
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Cited by 7 scholarly publications.
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KEYWORDS
Lithography

Etching

Personal protective equipment

Photomasks

Model-based design

Mask making

Semiconducting wafers

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