Use of silicon-versus-layout verification (SiVL) in process control of wafer lithography and mask-making metrology

Paul J. M. van Adrichem; Frank A. J. M. Driessen; Kees van Hasselt

doi:10.1117/12.485001

2 June 2003 Use of silicon-versus-layout verification (SiVL) in process control of wafer lithography and mask-making metrology

Paul J. M. van Adrichem, Frank A. J. M. Driessen, Kees van Hasselt

Author Affiliations +

Proceedings Volume 5038, Metrology, Inspection, and Process Control for Microlithography XVII; (2003) https://doi.org/10.1117/12.485001
Event: Microlithography 2003, 2003, Santa Clara, California, United States

Abstract

The latest generations of CMOS are being patterned at decreasing k1 values, which is one of the reasons that their process windows are decreasing. Hence, control of the process gets more and more important and in-die critical dimension (CD) measurements are gradually being introduced for the monitoring of the in-line lithographic process performance. Because an increasingly large portion of the CD-error-budget is already being consumed by the mask-making, there is also a strong tendency toward improving process control of the mask, which in turn leads to a rapid increase in the number of mask-CD measurements even within the die. The main two reasons for the larger contribution of the mask to the error budget at wafer level are: 1) the mask process itself, and 2) the mask-error enhancement factor (MEEF), the magnification factor of reticle-to-wafer error. The latter factor and its lithographic process dependence are very much depending on the shape of a feature and its local vicinity. For example a narrow dense binary line has a larger MEEF than an isolated line and its partial derivative to defocus is much larger. Hence it would make sense to relate such MEEF process-behaviour to the 2D layout shapes in the design and use that as a metric during mask qualification. In this work the Silicon-versus-layout verification (SiVL) tool- inherently an OPC evaluation tool- is used to find such features in the layout that will be most critical for the wafer lithographic process by automatic extraction and selection of their MEEF values. This information can then be used to generate realistic mask specifications and forms a cost-method to control both mask quality and price.

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Paul J. M. van Adrichem, Frank A. J. M. Driessen, and Kees van Hasselt "Use of silicon-versus-layout verification (SiVL) in process control of wafer lithography and mask-making metrology", Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); https://doi.org/10.1117/12.485001

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KEYWORDS

Photomasks

Computed tomography

Semiconducting wafers

Process control

Optical proximity correction

Lithography

Silicon

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