Optimizing manufacturability for the 65-nm process node

Dipankar Pramanik; Michel L. Cote

doi:10.1117/12.485248

10 July 2003 Optimizing manufacturability for the 65-nm process node

Dipankar Pramanik, Michel L. Cote

Proceedings Volume 5042, Design and Process Integration for Microelectronic Manufacturing; (2003) https://doi.org/10.1117/12.485248
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

The 65nm technology node will require a more detailed assessment of the tradeoffs between performance, manufacturability and cost than any previous generation of technology. Circuits fabricated at the 65nm technology node need to use Strong Phase shifting techniques such as Full-Phase and Model based OPC in order to guarantee printability of critical layers, such as the poly layer. We presents a methodology whereby layouts are genrated base don a preliminary set of design rules for 65nm and the process latitude determined using image simulation software. Mask costs were also estiamted base donfigure counts of the required masks. Tradeoffs between mask costs, manufacturibility and density were made by small changes to the design rules. The simultaneous use of tools that integrate the design creation process with mask generation allows far better optimization than current methodology where physical design is separated from the downstream data preparation and processing.

Citation Download Citation

Dipankar Pramanik and Michel L. Cote "Optimizing manufacturability for the 65-nm process node", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); https://doi.org/10.1117/12.485248

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