Multilevel clustering fault model for IC manufacture

Yu. I. Bogdanov; N. A. Bogdanova; A. V. Rudnev

doi:10.1117/12.562667

28 May 2004 Multilevel clustering fault model for IC manufacture

Yu. I. Bogdanov, N. A. Bogdanova, A. V. Rudnev

Proceedings Volume 5401, Micro- and Nanoelectronics 2003; (2004) https://doi.org/10.1117/12.562667
Event: Micro- and Nanoelectronics 2003, 2003, Zvenigorod, Russian Federation

Abstract

A hierarchical approach to the construction of compound distributions for process-induced faults in IC manufacture is proposed. Within this framework, the negative binomial distribution is treated as level-1 models. The hierarchical approach to fault distribution offers an integrated picture of how fault density varies from region to region within a wafer, from wafer to wafer within a batch, and so on. A theory of compound-distribution hierarchies is developed by means of generating functions. A study of correlations, which naturally appears in microelectronics due to the batch character of IC manufacture, is proposed. Taking these correlations into account is of significant importance for developing procedures for statistical quality control in IC manufacture. With respect to applications, hierarchies of yield means and yield probability-density functions are considered.

Citation Download Citation

Yu. I. Bogdanov, N. A. Bogdanova, and A. V. Rudnev "Multilevel clustering fault model for IC manufacture", Proc. SPIE 5401, Micro- and Nanoelectronics 2003, (28 May 2004); https://doi.org/10.1117/12.562667

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