Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array

Paul Chen; Mike Butts; Brad Budlong; Paul Wasson

doi:10.1117/12.797113

17 April 2008 Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array

Paul Chen, Mike Butts, Brad Budlong, Paul Wasson

Author Affiliations +

Proceedings Volume 6968, Signal Processing, Sensor Fusion, and Target Recognition XVII; 69681V (2008) https://doi.org/10.1117/12.797113
Event: SPIE Defense and Security Symposium, 2008, Orlando, Florida, United States

Abstract

This paper introduces a novel computing architecture that can be reconfigured in real time to adapt on demand to multi-mode sensor platforms' dynamic computational and functional requirements. This 1 teraOPS reconfigurable Massively Parallel Processor Array (MPPA) has 336 32-bit processors. The programmable 32-bit communication fabric provides streamlined inter-processor connections with deterministically high performance. Software programmability, scalability, ease of use, and fast reconfiguration time (ranging from microseconds to milliseconds) are the most significant advantages over FPGAs and DSPs. This paper introduces the MPPA architecture, its programming model, and methods of reconfigurability. An MPPA platform for reconfigurable computing is based on a structural object programming model. Objects are software programs running concurrently on hundreds of 32-bit RISC processors and memories. They exchange data and control through a network of self-synchronizing channels. A common application design pattern on this platform, called a work farm, is a parallel set of worker objects, with one input and one output stream. Statically configured work farms with homogeneous and heterogeneous sets of workers have been used in video compression and decompression, network processing, and graphics applications.

Citation Download Citation

Paul Chen, Mike Butts, Brad Budlong, and Paul Wasson "Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array", Proc. SPIE 6968, Signal Processing, Sensor Fusion, and Target Recognition XVII, 69681V (17 April 2008); https://doi.org/10.1117/12.797113

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

;

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE