Defect tolerant prefix adder design

Robert Moric; Braden J. Phillips; Michael J. Liebelt

doi:10.1117/12.814438

30 December 2008 Defect tolerant prefix adder design

Robert Moric, Braden J. Phillips, Michael J. Liebelt

Proceedings Volume 7268, Smart Structures, Devices, and Systems IV; 72680F (2008) https://doi.org/10.1117/12.814438
Event: SPIE Smart Materials, Nano- and Micro-Smart Systems, 2008, Melbourne, Australia

Abstract

This paper introduces a defect tolerant 64-bit Sklansky prefix adder, designed with the goal of increasing its reliability and extending its lifetime in the presence of hard faults. We consider defect tolerance for early transistor wear-out by exploring the design of fine-grained reconfigurable logic. The approach involves enabling spare processing elements to replace defective elements. Power gating techniques are used to disable faulty logic blocks and enable spare logic. Minimum sized transistors are used for spare processing elements to reduce area overhead, and simplify reconfiguration interconnect. The performance of the design is compared to a baseline, non-repairing design using the cost metrics of: area overhead, power consumption, and performance in the fault free and faulty case.

Citation Download Citation

Robert Moric, Braden J. Phillips, and Michael J. Liebelt "Defect tolerant prefix adder design", Proc. SPIE 7268, Smart Structures, Devices, and Systems IV, 72680F (30 December 2008); https://doi.org/10.1117/12.814438

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