Performance analysis of mixed communication architectures: bus and network-on-chip

Stefano Gigli; Massimo Conti

doi:10.1117/12.821547

28 May 2009 Performance analysis of mixed communication architectures: bus and network-on-chip

Stefano Gigli, Massimo Conti

Proceedings Volume 7363, VLSI Circuits and Systems IV; 73630M (2009) https://doi.org/10.1117/12.821547
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany

Abstract

System on Chip performances in terms of speed and power dissipation are becoming dominated by communication between the cores. The communication architectures are usually based on bus or Network on Chip. Bus-based on chip communication architectures are simple and flexible. Network on Chip is a distributed communication architecture allowing to overcome the bus bottleneck occurring when the number of cores connected is high. In this work we present the integration in a SystemC NoC library of a new library for creating and simulating master and slave devices of the AMBA AHB bus. The simulation environment has been used to evaluate the performance in terms of communication throughput and delay in different communication architectures: AMBA AHB bus, NoC and mixed.

Citation Download Citation

Stefano Gigli and Massimo Conti "Performance analysis of mixed communication architectures: bus and network-on-chip", Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630M (28 May 2009); https://doi.org/10.1117/12.821547

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