Paper
5 April 2012 Optimization of blended virtual and actual metrology schemes
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Abstract
There are two competing costs that occur in off line semiconductor processing metrology. One is the cost of operating the metrology tool, and the other is the loss in terms of processing cost and yield due to the time lapse between the occurrence and the correction of a process fault. Virtual metrology (VM) is an alternative scheme which takes data produced by the processing tool in real time (e.g. plasma etching data during isolation trench formation) and predicts an outcome of the wafer (e.g. critical dimension of the trench) utilizing an empirical model. Although VM prediction quality is not as good as that of conventional metrology, it produces an immediate, low cost prediction for each wafer going through a process. In real life, we envision that practical metrology schemes will involve a synergistic blend of VM and actual metrology, the latter being used for the needed periodic recalibration of the VM empirical model. In this work, we formulate the costs associated with Type I and Type II errors that result from a blended metrology scheme, and propose a general framework that can be used to quickly lead to the optimal design of such schemes given the characteristics of the process in question. We also explore the effects of a faulty process (by means of mean shift) on the cost analysis.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jae Yeon Claire Baek and Costas J. Spanos "Optimization of blended virtual and actual metrology schemes", Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 83241K (5 April 2012); https://doi.org/10.1117/12.916313
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CITATIONS
Cited by 6 scholarly publications and 2 patents.
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KEYWORDS
Metrology

Scanning electron microscopy

Semiconducting wafers

Data modeling

Statistical analysis

Time metrology

Error analysis

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