HVM metrology challenges towards the 5nm node

Benjamin Bunday

doi:10.1117/12.2218375

24 March 2016 HVM metrology challenges towards the 5nm node

Benjamin Bunday

Proceedings Volume 9778, Metrology, Inspection, and Process Control for Microlithography XXX; 97780E (2016) https://doi.org/10.1117/12.2218375
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

This paper will provide a high level overview of the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry. First, we will take a broad view of the needs of patterned defect, critical dimensional (CD/3D) and films metrology, and present the extensive list of applications for which metrology solutions are needed. Commonalities and differences among the various applications will be shown. We will then report on the gating technical limits of the most important of these metrology solutions to address the metrology challenges of future nodes, highlighting key metrology technology gaps requiring industry attention and investment.

Citation Download Citation

Benjamin Bunday "HVM metrology challenges towards the 5nm node", Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97780E (24 March 2016); https://doi.org/10.1117/12.2218375

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