Presentation + Paper
17 December 2024 Sub-3nm gate-all-around process incoming control and application of advanced EUV overlay strategy enhancing productivity
Author Affiliations +
Abstract
Overlay control for critical EUV lithography steps in MBCFET production poses significant challenges due to process-induced overlay errors. Previous correction methods assumed ideal wafer chucking conditions at the lithography step, which do not reflect the complex deformations and non-optimal chucking encountered in production environments. In this paper, we propose a powerful method to predictand correct process-induced overlay considering wafer warpage, backside surface roughness, and wafer chuck clamping residuals. Our model helps to accurately identify and correct the primary contributor to overlay errors. This offers a remarkable overlay control transition from wafer level corrections to chuck level corrections at the most critical lithography steps. This significant transition was possible due to warpage control at the ER step which suppressed overlay modeling variation by0.38nm (39%), leading to a 5.3% yield increase. This brings 26% reduction in EUV photo exposures and reduction of 2.5 overlay measurement tools per step, financial savings equivalent to $19.1 million USD yearly. This approach offers significant productivity improvements and is broadly applicable across various EUV lithography steps in MBCFET production and beyond.
Conference Presentation
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
SungWoon Uh, Dongmin Kim, Dooho Park, Sangil Son, JaeHyung Kim, and InSung Kim "Sub-3nm gate-all-around process incoming control and application of advanced EUV overlay strategy enhancing productivity", Proc. SPIE PC12953, Optical and EUV Nanolithography XXXVII, PC129530N (17 December 2024); https://doi.org/10.1117/12.3010035
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KEYWORDS
Semiconducting wafers

Overlay metrology

Surface roughness

Extreme ultraviolet

Extreme ultraviolet lithography

Process control

Deformation

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