KEYWORDS: Semiconducting wafers, Metals, Back end of line, Silver, Optical lithography, Transmission electron microscopy, Nanosheets, Front end of line, Wafer bonding, Semiconductors
The saturation in dimensional scaling has clearly impacted the semiconductor technology roadmap. The extension of patterning cliffs through new tools and multi-patterning lithography, as well as the introduction of innovative scaling boosters is helping in optimally scaling the Power-Performance-Area (PPA) metrics. However, because of the increase in the process complexity and reduced area benefits, manufacturing cost is increasing. Therefore, moving to a PPA-Cost (PPAC) methodology to monitor and analyze the cost of a technology is becoming increasingly necessary.
Wafer bonding is a key technology for many advanced chip technologies. For 3D integration, advanced stacking schemes and high-density packaging put a stringent requirement on the bonding reliability. Bonding quality can be characterized by the absence of voids at the bonding interface, as the voids delimit the complexity of the subsequent processing and integration steps. Therefore, in-line and non-destructive inspection techniques for void detection are crucial for early-stage detection and full process integration. In this work, we perform a comprehensive study on bonding void detection for 3D integration. We fabricate bonded Si wafers with programmed bonding voids with size from 10 nm to 20 μm. We combine different inspection and review tools, including acoustic, optical, electron beam etc., for bonding void detection at different process steps of the fabrication with different top Si thicknesses.
Marc Heyns, Florence Bellenger, Guy Brammertz, Matty Caymax, Mirco Cantoro, Stefan De Gendt, Brice De Jaeger, Annelies Delabie, Geert Eneman, Guido Groeseneken, Geert Hellings, Michel Houssa, Francesca Iacopi, Daniele Leonelli, Dennis Lin, Wim Magnus, Koen Martens, Clement Merckling, Marc Meuris, Jerome Mitard, Julien Penaud, Geoffrey Pourtois, Marc Scarrozza, Eddy Simoen, Bart Soree, Sven Van Elshocht, William Vandenberghe, Anne Vandooren, Philippe Vereecke, Anne Verhulst, Wei-E Wang
The use of high mobility channel materials such as Ge and III/V compounds for CMOS applications is being explored.
The introduction of these new materials also opens the path towards the introduction of novel device structures which
can be used to lower the supply voltage and reduce the power consumption. The results illustrate the possibilities that are
created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.
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