KEYWORDS: Etching, Plasma etching, Plasma, Climate change, Gases, Transistors, Power consumption, Front end of line, Sustainable technology, CMOS technology
The semiconductor industry is aware of its high resource consumption and overall impact on the environment and is working to minimize it. Especially, the use of perfluorocarbons (PFC) during the dry etching and deposit steps of device manufacturing is a major concern because of the extremely high global warming potential (GWP) and lifetime of most of those compounds. Consequently, plasma etching significantly contributes to CO2 emissions for sub-28nm technologies on Scope 1 and 2 emissions. Currently, CEA-Leti is developing a 10nm node on FDSOI (Fully Depleted Silicon On Insulator) technology. In this framework, we present Life Cycle Assessment (LCA) of etching processes for FDSOI transistor technologies. A comparison of impacts between the 28nm node and 10 nm one is then conducted for FEOL and MEOL processes. Finally, based on these results, some eco-innovation proposals are discussed.
Hierarchical structures that combine microlens arrays and nanostructures exhibit exceptional potential in enhancing optical characteristics of optoelectronic devices. Furthermore, multi-scale architectures confer multifunctional capabilities to these devices. Existing methodologies for creating hierarchical structures can be classified by the initial structure fabricated: the "microfirst" and "nanofirst" approaches. Among these, the nanofirst strategy stands out as the most versatile, despite presenting challenges in 3D micropatterning on existing nanostructured surfaces. However, it leads to a greater challenge involving 3D micropatterning on existing nanostructured surfaces. To address this challenge, we propose a novel technique for fabricating hierarchical 3D microstructures through controlled bending of suspended microdisks. This method offers new perspectives on achieving hierarchical structures and 3D microstructures.
DUV photolithography, as the major process of nanofabrication, typically requires high volumes of toxic chemicals within resist formulation, solvent and developer. In this context, alternative chemistries to current petroleum-derived photoresists are proposed to reduce environmental impacts. Chitosan represents a bio-sourced resist allowing water-based patterning processes free of organic solvent and alkali-based developers, by substitution with a green solvent (deionized (DI) water). This paper present last stepwise process in the patterning integration with a chitosan-based resist. Preliminary results using a 300 mm pilot line scale at CEA-Leti demonstrate patterns resolution down to 800 nm along with plasma etch transfer into Si substrate. Finally, the environmental impact through life cycle analysis (LCA) of the whole process based on chitosan resist is assessed and compared to conventional solvent-based processes.
Densification and reduction of lithographic features sizes keeping low defectivity is one of the biggest challenges in the patterning area. In order to extend 193 immersion capabilities and meet advanced applications needs, multi exposure image mode is a promising option for non-high volume manufacturing. It allows from a unique pattern with a fixed critical dimension (CD) and pitch, to obtain more dense patterns in a large surface without any process loop of standard flow, a huge benefit compared to litho-etch-litho-etch (LELE) approach. The study carried out explores this method with a specific design of pillars array printed using Negative Tone Development (NTD). The multi-image option relies on exposing multiple times the same initial pattern with a low image-to-image overlay. Based on intrinsic scanner performances, imageto-image placement error should be less than two nm. In this paper, many functionalities are explored to customize patterns from a single and unique mask design. One stake is to transfer (into silicon) a 2 mm * 2 mm pillar array design with a pitch divided by two, covering a wide surface on a 300 mm wafer and answering overlay and stitching requirements. Final results give well defined pillars which intra-wafer CD uniformity (3σ) satisfies application process requests. By using a flexible multi-image mode, mask constraints (cost and quality) can be relaxed, i.e. with a larger pitch structure on the reticle than the targeted one, final feature can be achieved. This development can be extended to hybrid lithography such as NanoImprint Lithography (NIL) or specific applications such as optics.
KEYWORDS: Directed self assembly, Lithography, Line width roughness, Nanoimprint lithography, Semiconducting wafers, Etching, Electron beam lithography, System on a chip, Critical dimension metrology, Photoresist processing
In the lithography landscape, EUV technology recovered some credibility recently. However, its large adoption remains uncertain. Meanwhile, 193nm immersion lithography, with multiple-patterning strategies, supports the industry preference for advanced-node developments. In this landscape, lithography alternatives maintain promise for continued R&D. Massively parallel electron-beam and nano-imprint lithography techniques remain highly attractive, as they can provide noteworthy cost-of-ownership benefits. Directed self-assembly lithography shows promising resolution capabilities and appears to be an option to reduce multi-patterning strategies. Even if large amount of efforts are dedicated to overcome the lithography side issues, these solutions introduce also new challenges and opportunities for the integration schemes.
Overcoming the optical limitations of 193-nm immersion lithography can be achieved using directed self-assembly (DSA) of block-copolymers (BCPs) as a low-cost and versatile complementary technique. The goal of this paper is to investigate the potential of DSA to address line and space (L/S) high-resolution patterning by performing the density multiplication of lines with the graphoepitaxy approach. As surface affinity is a key parameter in self-assembly, three variations, or “flavors,” of DSA template affinity are investigated regarding several success criteria such as morphology control or defectivity. More precisely, both the methodology to register DSA defects and the impact of process parameters on defectivity are detailed. Using the 300-mm pilot line available in LETI and Arkema’s advanced materials, we investigate process optimization of DSA line/space patterning of a 38-nm period lamellar PS-b-PMMA BCP (L38). Our integration scheme is based on BCP self-assembly inside organic hard mask guiding patterns obtained using 193i-nm lithography. Defect analysis coupled with the fine tuning of process parameters (annealing, brush material) provided the optimum conditions for the L38 self-assembly. Using such conditions, DSA using the three affinity flavors is investigated by means of SEM top-view and cross-section review. Lithographic performances of one selected flavor are then evaluated with the comparison of process windows function of either commensurability, morphology, or roughness. This work is meant as a guideline for the graphoepitaxy optimization of materials and process parameters on a 300-mm platform.
For sub-10nm technologies, the semiconductor industry is facing the limits of conventional lithography to achieve narrow dimensions. DSA (Directed Self-Assembly) of Block Copolymers (BCP) is one of the most promising solutions to reach sub-10nm patterns with a high density. One challenge for DSA integration is the removal of PMMA selectively to PS. In this paper, we propose to study PMMA removal selectively to PS by screening different plasma etch chemistries. These chemistries developed on blanket wafers have been tested on cylindrical and lamellar patterned wafers.
In this paper, we focus on the directed-self-assembly (DSA) application for contact hole (CH) patterning using polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymers (BCPs). By employing the DSA planarization process, we highlight the DSA advantages for CH shrink, repair and multiplication which are extremely needed to push forward the limits of currently used lithography. Meanwhile, we overcome the issue of pattern densityrelated- defects that are encountered with the commonly-used graphoepitaxy process flow. Our study also aims to evaluate DSA performances as function of material properties and process conditions by monitoring main key manufacturing process parameters: CD uniformity (CDU), placement error (PE) and defectivity (Hole Open Yield = HOY). Concerning process, it is shown that the control of surface affinity and the optimization of self-assembly annealing conditions enable to significantly enhance CDU and PE. Regarding materials properties, we show that the best BCP composition for CH patterning should be set at 70/30 of PS/PMMA total weight ratio. Moreover, it is found that increasing the PS homopolymer content from 0.2% to 1% has no impact on DSA performances. Using a C35 BCP (cylinder-forming BCP of natural period L0 = 35nm), high DSA performances are achieved: CDU-3σ = 1.2nm, PE-3σ = 1.2nm and HOY = 100%. The stability of DSA process is also demonstrated through the process follow-up on both patterned and unpatterned surfaces over several weeks. Finally, simulation results, using a phase field model based on Ohta-Kawasaki energy functional are presented and discussed with regards to experiments.
Overcoming the optical limitations of 193nm immersion lithography can be achieved using Directed Self Assembly (DSA) of block-copolymers (BCPs) as a low-cost and versatile complementary technique. The goal of this paper is to investigate the potential of DSA to address line and space (L/S) high resolution patterning by performing the density multiplication of lines with the graphoepitaxy approach. As surface affinity is a key parameter in self-assembly, three variations, or "flavors", of DSA template affinity are investigated regarding several success criteria such as morphology control or defectivity. More precisely, both the methodology to register DSA defects and the impact of process parameters on defectivity are detailed. Using the 300mm pilot line available in LETI and Arkema’s advanced materials, we investigate process optimization of DSA line/space patterning of a 38nm period lamellar PS-b-PMMA BCP (L38). For this study, our integration scheme, depicted in figure 2-1, is based on BCP self-assembly inside organic hard mask guiding patterns obtained using 193i nm lithography. Defect analysis coupled with the fine tuning of process parameters (annealing, brush material) provided the optimum conditions for the L38 self-assembly. Using such conditions, DSA using the three affinity flavors is investigated by means of SEM top-view and cross-section review. Lithographic performances of one selected flavor are then evaluated with the comparison of Process Windows (PWs) function of either commensurability, morphology or LWR. This work is a first step in finding the best process for an industrial graphoepitaxy approach.
Directed Self-Assembly (DSA) of Block Copolymers (BCP) is one of the most promising solutions for sub-10 nm nodes. However, some challenges need to be addressed for a complete adoption of DSA in manufacturing such as achieving DSA-friendly design, low defectivity and accurate pattern placement. In this paper, we propose to discuss the DSA integration flows using graphoepitaxy for contact-hole patterning application. DSA process dependence on guiding pattern density has been studied and solved thanks to a new approach called “DSA planarization”. The capabilities of this new approach have been evaluated in terms of defectivity, Critical Dimension (CD) control and uniformity before and after DSA etching transfer.
We discuss here different strategies for making arrays of Au nanoparticles using copolymer templates. Top-down and
bottom-up routes are considered and the optical properties of as-prepared Au nanoparticles are discussed and compared
to numerical simulations. Potential for applications such as biosensors or strain sensors is also assessed.
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