We report inspection results of EUVL masks with 193nm wavelength tools for 30nm and 24nm half-pitch nodes. The
dense line and space and contact pattern is considered to study inspection capability. The evaluation includes defect
contrast variation depending on illumination conditions, defect types, and design nodes. We show many inspection
images with various optic conditions. Consequently, the detection sensitivity is affected by contrast variation of defects.
The detection sensitivity and wafer printability are addressed with a programmed defect mask and a production mask.
With these results, we want to discuss the capability of current EUVL mask inspection tools and the future direction.
Printability and inspectability of phase defects in EUVL mask originated from substrate pit were investigated. For
this purpose, PDMs with programmed pits on substrate were fabricated using different ML sources from several
suppliers. Simulations with 32-nm HP L/S show that substrate pits with below ~20 nm in depth would not be printed on
the wafer if they could be smoothed by ML process down to ~1 nm in depth on ML surface. Through the investigation of
inspectability for programmed pits, minimum pit sizes detected by KLA6xx, AIT, and M7360 depend on ML smoothing
performance. Furthermore, printability results for pit defects also correlate with smoothed pit sizes. AIT results for
patterned mask with 32-nm HP L/S represents that minimum printable size of pits could be ~28.3 nm of SEVD. In
addition, printability of pits became more printable as defocus moves to (-) directions. Consequently, printability of
phase defects strongly depends on their locations with respect to those of absorber patterns. This indicates that defect
compensation by pattern shift could be a key technique to realize zero printable phase defects in EUVL masks.
The particle removal efficiency (PRE) of cleaning processes diminishes whenever the minimum defect size for a specific
technology node becomes smaller. For the sub-22 nm half-pitch (HP) node, it was demonstrated that exposure to high
power megasonic up to 200 W/cm2 did not damage 60 nm wide TaBN absorber lines corresponding to the 16 nm HP
node on wafer. An ammonium hydroxide mixture and megasonics removes ≥50 nm SiO2 particles with a very high PRE.
A sulfuric acid hydrogen peroxide mixture (SPM) in addition to ammonium hydroxide mixture (APM) and megasonic is
required to remove ≥28 nm SiO2 particles with a high PRE. Time-of-flight secondary ion mass spectroscopy (TOFSIMS)
studies show that the presence of O2 during a vacuum ultraviolet (VUV) (λ=172 nm) surface conditioning step will result
in both surface oxidation and Ru removal, which drastically reduce extreme ultraviolet (EUV) mask life time under
multiple cleanings. New EUV mask cleaning processes show negligible or no EUV reflectivity loss and no increase in
surface roughness after up to 15 cleaning cycles. Reviewing of defect with a high current density scanning electron
microscope (SEM) drastically reduces PRE and deforms SiO2 particles. 28 nm SiO2 particles on EUV masks age very
fast and will deform over time. Care must be taken when reviewing EUV mask defects by SEM. Potentially new
particles should be identified to calibrate short wavelength inspection tools. Based on actinic image review, 50 nm SiO2
particles on top of the EUV mask will be printed on the wafer.
Naturally occurring sub 30 nm defects on quartz and Low Thermal Expansion Material (LTEM) substrates were characterized by using Atomic Force Microscope(AFM). Our data indicates that a majority of defects on the incoming substrate are hard defects including large, flat particles with a height less than 5 nm, tiny particles with a size of 10 nm to 30 nm SEVD and pits with a depth of about 9 nm. All the soft particles added by handling with sizes of >50 nm can be removed with a single cleaning process. At least four cleaning cycles are required to remove all of the remaining embedded particles. However, after particle removal in their initial location a shallow pit remains. Based on detailed characterization of defect and surface by AFM, we propose that these hard particles are added during the glass polishing step and therefore it is important to revisit the glass Chemical Mechanical Polishing (CMP) processes and optimize them for defect reduction. A qualitative value for particle removal efficiency (PRE) of >99% was obtained for 20 nm Poly Styrene Latex Sphere (PSL) deposited particles on surface of glass.
As we approach the 22nm half-pitch (hp) technology node, the industry is rapidly running out of patterning options. Of
the several lithography techniques highlighted in the International Technology Roadmap for Semiconductors (ITRS), the
leading contender for the 22nm hp insertion is extreme ultraviolet lithography (EUVL). Despite recent advances with
EUV resist and improvements in source power, achieving defect free EUV mask blank and enabling the EUV mask
infrastructure still remain critical issues. To meet the desired EUV high volume manufacturing (HVM) insertion target
date of 2013, these obstacles must be resolved on a timely bases. Many of the EUV mask related challenges remain in
the pre-competitive stage and a collaborative industry based consortia, such as SEMATECH can play an important role
to enable the EUVL landscape. SEMATECH based in Albany, NY is an international consortium representing several of
the largest manufacturers in the semiconductor market. Full members include Intel, Samsung, AMD, IBM, Panasonic,
HP, TI, UMC, CNSE (College of Nanoscience and Engineering), and Fuller Road Management. Within the
SEMATECH lithography division a major thrust is centered on enabling the EUVL ecosystem from mask development,
EUV resist development and addressing EUV manufacturability concerns. An important area of focus for the
SEMATECH mask program has been the Mask Blank Development Center (MBDC). At the MBDC key issues in EUV
blank development such as defect reduction and inspection capabilities are actively pursued together with research
partners, key suppliers and member companies. In addition the mask program continues a successful track record of
working with the mask community to manage and fund critical mask tools programs. This paper will highlight recent
status of mask projects and longer term strategic direction at the MBDC. It is important that mask technology be ready to
support pilot line development HVM by 2013. In several areas progress has been made but a continued collaborative
effort will be needed along with timely infrastructure investments to meet these challenging goals.
We have explored substrate effects upon the characteristics of haze creation on the mask surface by
performing surface analysis for each of Cr, MoSiON, and Qz substrates of the mask before and after laser exposure. We
found out chemical ions such as sulfur and ammonium ions should have different mobility behavior towards haze defect
creation depending on each substrate during laser exposure. This fact can partially clarify the reason why haze
occurrence on the mask in real mass production mainly comes up with Qz substrate surface even though it has the lowest
level of chemical residue on it. We also realized that sulfur ions are penetrating into a sub layer of Qz substrate and even
deeper during laser exposure, which signifies that we may have to remove a thin surface layer from Qz substrate to
further improve haze issue from the current standpoint.
We created haze defects on the PSM mask surface using ArF haze accelerator while the mask was
previously cleaned by SPM and SC1 solutions. Then we directly analyzed the defects on the surface using TOF-SMS.
The comprehensive analysis of TOF-SIMS signifies that the defects mainly consist of hydrocarbons, Na, K, Cl, F, Mg,
Al, etc., which have probably come from previous procedures, fab environments, storage materials, handling steps, or
pellicle materials. This fact implies the exclusion of sulfate or ammonium ions from the mask surface should not be
enough for the realization of haze-free PSM masks. In addition, complete removal of residual hydrocarbons deposited
through previous procedures and perfect protection against environmental contaminants from fab air, storage materials,
handling steps, or pellicle materials should be further accomplished.
As the design rule continues to shrink towards 45 nm node and beyond, the lithographers need the new technologies such as immersion lithography and EUV lithography. Also the inspection specification on the printed reticle defects is becoming even more challenging for the reticles used in both lithography methods.
The main purpose of this study is to investigate the pattern defect detection capability on EUV mask with the memory design patterns of 45 nm node and below in the DUV reticle inspection systems at our mask-shop and to compare those results with the absorber defect specification from the EUV lithography simulation in those design rules.
In addition, we investigate the inspection capability on the pattern defects with the test optical mask designed in 45 nm node and below for the immersion lithography and compare the defect detection ability on the EUV mask and the optical mask in the current DUV reticle inspection equipment.
The shrink of device node to 65 and 45nm node masks mask manufacturers paying their attention to repair process in
terms of mask cost efficiency. Thus, it is very important to define the repair performance accurately and introduce
adequate tools timely. Usually the repair performance has been expressed as an edge placement error, transmittance
change and quartz damage. We have used the measuring tools such as CD SEM, AFM and AIMS to measure those
factors and the 2D simulator, Solid C to predict the repair performance. In this case, 3D topographical effect is not
considered. However, the 3D topography of pattern becomes quite important for 45 nm node or less.
ArF immersion lithography is the strongest candidate for the 45 nm node. The immersion technology makes it
possible to use of hyper NA systems1. Hyper NA will increase the polarization effect of illumination source2. Therefore,
the topography of pattern is quite important with respect to the intensity and the polarization of various diffraction
orders. This paper presents repair specifications based on the Solid E 3D simulator of the 45 nm node.
It is important to understand how the outgassed chemicals from pellicle materials are involving in various
surface reactions towards haze defect formation on the mask surface during the exposure. In this work, we have
analyzed the gaseous environment and the substrate surface under laser exposure in the specially designed quartz tube
filled by air, or N2. We observed that various chemicals that consist of the pellicle film are outgassed from the film and
then deposited or interact with other chemicals to make haze defects on the substrate surface during laser exposure.
This fact can be further applied not only to the study of pellicle outgassing effect on haze defect growth mechanism but
also to the development of real-time monitoring tools for the defect growth progress on the mask surface.
With the use of 193nm lithography, time-dependent haze problem has become a critical issue for semiconductor industry. The understanding of the conditions that create haze defects is very crucial for the future development of haze-free cleaning processes. The gaseous environment trapped between the pellicle film and the mask surface triggers photochemical reaction under laser exposure, which could result in the formation of killer (printable) defects on the mask surface. Therefore, the real time analysis of the haze environment in the trapped space could provide essential clues to the characterization of haze defect growth mechanism. This fundamental study can be applied to the invention of real-time monitoring tools for the defect growth progress on the mask surface as well as the development of haze-free cleaning processes. Here, we propose a method to analyze the gaseous space trapped between the pellicle film and the mask surface that creates a highly reactive environment.
As the design rule continues to shrink towards 65nm size and beyond the defect criteria are becoming ever more challenging. Pattern fidelity and reticle defects that were once considered as insignificant or nuisance are now becoming significant yield impacting defects. The intent of this study is to utilize the new generation DUV system to compare Die-to-Die Reflected Light inspection and Die-to-Die Transmitted Light Inspection to increase defect detection for optimization of the 65nm node process.
In addition, the ReviewSmart will be implemented to help categorically identify systematic tool and process variations and thus allowing user to expedite the learning process to develop a production worthy 65nm node mask process. The learning will be applied to Samsung's pattern inspection strategy, complementing Transmitted Light Inspection, on critical layers of 65 nm node to gain ability to find defects that adversely affect process window.
CD(Critical Dimension) Non-Uniformity on a mask is normally separable into global and local CD errors by means of their error sources. In general a global CD error trend on a mask shows the properties of each process. On the other hand, local CD errors on a mask are pretty much random and caused from mainly measurement errors, LER(Line Edge Roughness), and litho-shot errors. However, because of its difficulty to pin point the sources of errors and correct them, the local CD errors are required more attention. A Global CD error trend on a mask can be classified into several groups. One originating from vacuum delay, lithography error, bake and etch process will cause a side error trend on a mask. Others are fogging, radial trends of develop, and etch loading. In order to classify all those global CD errors and local CD errors, the proper monitoring mask must be required. The works on this paper mainly focalize on minimizing global CD error trends on a mask by separating and analyzing error components with proper monitoring system of each process. We therefore, provide a monitoring mask designed for efficiently representing global and local CD errors in more detailed fashion which can analyze CD errors of each process and make feed-back to each process in order to improve each process of mask manufacturing.
In this article, we will analyze in-field uniformity (IFU) fluctuation of linewidth on wafer considering errors related to mask pellicle process. As gate linewidth becomes smaller, the controllability of in-field uniformity (IFU) plays a key role in wafer manufacturing yield. IFU depends on various lithography parameters including mask CD (critical dimension) uniformity, MEEF (mask error enhancement factor), exposure margin, focus margin, transmittance, flare and illumination uniformity. Although the short term repeatability of IFU is manageable, various parameters which affect IFU are still changing. During the wafer process, mask re-pellicle process is unavoidable due to haze contamination. For this reason, mask pellicle process including cleaning should be carefully controlled to achieve the long-term IFU stability on wafer as well as exposure machine (optic), resist coating (resist property). This paper will discuss the various experimental works including IFU correlation on wafer in terms of optic stability, resist stability and mask pellicle process. CD uniformity data on mask and IFU data on wafer is obtained from optical measurement tool to reduce measurement error disregarding local CD variation.
In this article, we analyzed in-field uniformity (IFU) on wafer considering exposure margin [linewidth variation (nm) per % exposure dose variation (%)] and the MEEF (mask error enhancement factor). As gate linewidth becomes smaller, the controllability of in-field uniformity (IFU) plays a key role in wafer manufacturing yield. IFU depends on various lithography parameters including mask CD (critical dimension) uniformity, MEEF, exposure margin, focus margin, transmittance, flare and illumination uniformity. In real world, the combination of wafer exposure machine and mask characteristics should be carefully considered to achieve better IFU on wafer. This presentation discusses the various experimental works including CD uniformity on mask, IFU on wafer, MEEF, exposure margin and wafer exposure machine. CD uniformity data on mask and IFU data on wafer is obtained from optical measurement tool to reduce measurement error disregarding local CD variation. Even though one handles a unit pattern, various MEEF exists in a unit pattern in case of complex pattern. In addition, the MEEF varying with the area across one mask degrades IFU on a wafer. IFU on a wafer is predictable using mask CD uniformity and exposure margin mean. Variation of exposure margin is the measure of stability of photo process. In manufacturing devices, mask and Litho. Tool should be well harmonized to achieve better IFU and a higher manufacturing yield. The photo process including resist process should be well controlled to get stability, as well as mask CD uniformity.
In mask-making process with e-beam lithography, the process stabilization can be evaluated by looking at the fluctuation of critical dimension (CD) uniformity, mean to target(MTT), and defect controllability. Among them, the capability of CD uniformity and mean to target depends strongly on the acceleration voltage of an exposure machine. Generally, a high acceleration voltage has advantages on dose latitude, pattern fidelity and CD linearity due to its small forward scattering range. Therefore, those merits using a high acceleration voltage can provide a higher yield for production photomask. In this paper, we have examined the CD uniformity and the MTT capability for production photomask fabrication in order to compare the process stabilization between 50 keV and 10 keV. By choosing a 50 keV exposure, significant improvements can be made in CD uniformity and MTT capability.
In mask-making process with e-beam lithography, the process capability is usually affected by exposure profile, resist contrast and development process. Dose latitude depends significantly on these three parameters. In this work, dose latitude between different resist contrasts has been experimentally studied as a function of linewidth, dose, beam size and over development magnitude using commercial PBS and ZEP 7000 resist on a photomask with 10 keV exposure. It has been found that ZEP 7000 resist with high contrast shows lower dose latitude, more sensitivity to the variation of linewidth, dose and beam size except for over development magnitude due to its relatively longer development time.
As optical lithography will be extended to device generations below 150 nm of design rule, the critical dimension (CD) uniformity on a photomask is required to be as small as 13 nm (3(sigma) ). The relationship between development method and dark erosion is discussed in view of CD variations. The temperature variation on a photomask is found to be more than 4 degrees Celsius for a conventional spin-spray development. An optimized process using a 'puddle process' to minimize developer temperature effect and non-uniform spray pressure effect on CD variation. The CD uniformity using the optimized process brings 11 nm in 3(sigma) over 127 mm X 127 mm area on a 6-inch mask.
In this paper we present results of the application of the GHOST technique to the practical use with 10 keV system. Three commercial e-beam resists which include ZEP7000, PBS, and EBR9 HS31 are selected for comparisons. The background dose equalization by the GHOST technique was found to be effective in reducing the proximity effect. It is generally assumed that exposure contrast degradation due to secondary exposure with largely defocused beam for the GHOST technique, especially at boundary between pattern pixel and nonpattern pixel, leads to poor CD uniformity. Thus, we examined CD uniformity variations as a function of with and without the GHOST technique for three e-beam resists .And we also reported the comparison of proximity effect correction quality for three resists by looking at CD linearity in order to investigate relationship between proximity effect and resist contrast.
Monte Carlo calculations, including secondary electron generation and development simulation, using a string algorithm have been carried out in order to estimate the process capabilities for a beam voltage of 50 keV with a rectangular shaped beam in electron beam lithography technology. The results for minimum resolution for the threshold energy density model and the development model were compared. A study of minimum resolution and process latitude with respect to the acceleration voltage, resist thickness, beam blur for commercial PBS resist was investigated. In addition, at 50 keV, the effects of (alpha) value, asymptotic slope at very high dose in the dissolution rate equation on minimum resolution and process latitude were examined. The results show that it is necessary to use resist with a higher (alpha) value, as well as a high acceleration voltage of 50 keV, in order to enhance process capabilities.
KEYWORDS: Photomasks, Manufacturing, Optical simulations, Monte Carlo methods, Scattering, Convolution, Lithography, 3D modeling, Electron beams, Scanning electron microscopy
A three-dimensional electron-beam lithography simulator version 2.0 has been newly enhanced for the multiple exposure of the Gaussian round beam. Development model parameters of the poly(butene-1-sulfone) positive electron beam resist in the spin-spray type are extracted through the experiment and simulation. With these parameters, electron beam simulation is applied to the submicron photomask manufacturing. The Gaussian round beam with the spot size and the address size of 0.1 micrometer is exposed with the dose of 2 (mu) C/cm2 at 10 keV on the 4000 angstrom resist/1000 angstrom chrome/glass substrate and the development time is 50 sec. With respect to the CD linearity of L/S, an isolated line and space pattern, the two-dimensional simulation results agree well to the measured data. The three dimensional simulation for a contact hole test pattern of gigabit DRAMs is demonstrated and compared with the SEM micrograph of the experimental profile. The results show that this simulation approach is highly practical to photomask manufacturing applications.
Owing to spin process used for mask manufacturing, the CD difference can be inevitably made in the radial direction by the centrifugal force. This difference can degrade CD uniformity of the given mask. So the ability of good maskmaking is closely related to the reduction of this difference as much as possible. In this paper, the CDCM (Critical Dimension Correction Method) is proposed. First, CD tendency of the given mask is mapped out. Then overall CD correction is done by making additional exposure for dose correction on the relatively underdeveloped CD region. The CDCM can also give some possibilities of improving wafer resolution by applying to the underdeveloped CD patterns on the wafer which are not corrected by layout design.
The main issue for fabricating a conventional Cr Mask with e-beam exposure system is a resolution limitation. Required minimum Critical Dimension (CD) goes down to below 1.0 μm on 4 X reticle, sometimes down to below 0.5 μm for OPC pattern. The resist which widely used in E-beam lithography is positive tone PBS. PBS has used in wet chrome etching process with spin spray or dip methods, due to its lack of resistance to dry etch durability. However, the isotropic process of wet chrome etching results in undercutting of the chrome. Thus, undercut causes the differences of CD between after development and final mask image. The purpose of this study is to decrease undercutting so that CD error can be minimized and a lot of rooms for overdevelopment margin can be obtained. CD linearity in case of below 1.0 μm was also investigated in detail. For this study, the chrome thickness coated on 6 x 6 x 250 mil PBS chrome plates was reduced. As a result of our study, we found that overdevelopment is marginal for the same final CD when using the thinner Cr, due to undercutting reduced. Good CD uniformity has been also achieved with good CD linearity.
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