High-resolution EUV mask patterning capability has been one of the key factors to enable sub-10nm nanofabrication. Especially, the emergence of the Multi-Beam Mask writer (MBMW) in photomask lithography was a breakthrough for achieving the write time independent of pattern complexity with fine resolution, opening the EUV era. However, as the transition towards high-NA EUV technology is ongoing to extend Moore’s law beyond 2nm-node and over, the novel exposure system challenges photomask manufacturing for higher resolution, accurate patterning fidelity and higher overlay due to 40% reduced resolution limit. Therefore, development of photomask lithography technologies including improved mask writer, photoresist, new materials of the substrate, and optimized EUV process is necessary to meet the desired minimum feature size and local fidelity such as local CDU, line edge roughness (LER) etc. In this paper, we aim to establish the evaluation method for optimized photomask process in upcoming high-NA EUV era. We analyze the budget of each factor contributing to EUV mask patterning performance including locality and resolution, and evaluate the total process window using MBMW. Finally, we discuss the comprehensive requirements and strategies on MBMW technology and relevant process to satisfy the mask patterning in the next generations from EUV mask maker's point of view.
Multibeam mask writers(MBMW) have been rapidly occupying on the field of leading edge EUV mask patterning for last several years. Thanks to outstanding ability of MBMW characteristics, sophisticated mask patterns and higher local pattern fidelity with low sensitivity E-beam resist can be realized in EUV era. Now most mask makers want to make good use of MBMW as a standard of making high-end grade masks such as Memory, Logic chips and etc. For this reason, they require higher pattern accuracy, faster writing time, higher data handling efficiency and matured machine stability aiming for the innovative mask making environment. Moreover, Larger coverage is needed as well not only for Low/High-NA EUV masks but also for even ARF masks.
In this paper, we touch key items with regard to comprehensive requirements from the mass production's point of view, for the versatile machines, several works and challenges to overcome on MBMW will be discussed.
Multi-beam mask writer MBM-1000 is developed for N5. It is designed to accomplish higher throughput than a singlebeam
VSB writer EBM-9500 at shot count higher than 500 G/pass, and write masks with low sensitivity resist to have
better CDU and patterning resolution. Product version of blanking aperture array (BAA) for MBM-1000 is fabricated
along with data transfer system to accomplish data rate of 300 Gbps. They have been integrated with writing control
software based on MBF format, a tool-specific format which handles any-angle pattern and polygon patterns. Writing
test without re-adjustment of beam current showed that exposure time control by BAA blanking is very stable, and linear
CD drift is less than 0.1 nm for 10 hours. Complex OPC pattern and ring pattern were printed on low-sensitivity pCAR
resist and showed good resolution to resolve 25 nm isolated line.
Multi-beam mask writer is under development to solve the throughput and patterning resolution problems in
VSB mask writer. Theoretically, the writing time is appropriate for future design node and the resolution is
improved with multi-beam mask writer. Many previous studies show the feasible results of resolution, CD
control and registration. Although such technical results of development tool seem to be enough for mass
production, there are still many unexpected problems for real mass production.
In this report, the technical challenges of multi-beam mask writer are discussed in terms of production and
application. The problems and issues are defined based on the performance of current development tool
compared with the requirements of mask quality. Using the simulation and experiment, we analyze the specific
characteristics of electron beam in multi-beam mask writer scheme. Consequently, we suggest necessary
specifications for mass production with multi-beam mask writer in the future.
KEYWORDS: Photomasks, Extreme ultraviolet, Scattering, Monte Carlo methods, Ray tracing, Electron beam lithography, Molybdenum, Metals, Ion beams, Laser scattering
The ray tracing of electron based on Monte Carlo is simulated by GEANT software to investigate the electron scattering
property in ArF photomask and EUV photomask. By Monte Carlo simulation, we have presented the mechanism of
electron scattering in EUV photomask and simulated the electron distribution which gives rise to change the patterning
performance of EUV photomask, compared with those of ArF photomask. Furthermore, the overlay error of EUV
photomask has been analyzed by the charging model.
EUV photomask has the additional electron distribution in the range of 2um, which comes from the strong electron
scattering at Mo/Si multilayer. Because of this additional electron distribution, EUV photomask has the pattern size
error due to proximity effect of electron when the conventional Gaussian function is used to correct the proximity effect
of ArF photomask. The maximum residual error due to the proximity effect in EUV photomask is 7nm. Furthermore, we
have confirmed that the linearity of pattern size is so different from ArF photomask and it is well explained with the
Gaussian blur model based on the electron distribution of EUV photomask.
Thinner absorber structure in EUVL mask is supposed to be applied in 2x HP node since it shows several
advantages including H-V bias reduction. Here, lithographic performances of EUVL masks as a function of absorber
stack height are investigated using ADT exposure experiments. Wafer SEM images show that minimum resolution is
almost identical at ~27.5 nm with absorber thickness ranging from 45 to 70 nm. Simulations also exhibit that NILS and
contrast become maximized and saturated in those ranges. However, thinner absorber structure using 50-nm-thick
absorber shows much lower H-V bias than conventional structure using 70-nm-thick absorber. MEEF, EL, DOF, and
LWR are also slightly improved with thinner absorber. One of the noticeable issues in thin absorber is low OD which
results in pattern damages and CD reduction at shot edges due to light leakage from the neighboring exposures. To
overcome these issues, appropriate light shielding process during mask fabrication as well as minimizing OoB radiation
in EUVL scanner are required. Another item to prepare for 2x HP node is to increase defect detection sensitivity with
19x nm inspection tools. Thus, absorber stacks with new ARC layer optimized for 19x nm inspection should be
developed and applied in EUVL mask blanks.
The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography
(EUVL) into high volume manufacturing, yet little data is available for understanding native defects on real masks. In
this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The
printability of defects and identification of their source from mask fabrication to handling were studied using wafer
inspection. The printable blank defect density excluding particles and patterns is 0.63/cm2. Mask inspection is shown to
have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus
analysis and a different wafer stack.
Printability and inspectability of phase defects in EUVL mask originated from substrate pit were investigated. For
this purpose, PDMs with programmed pits on substrate were fabricated using different ML sources from several
suppliers. Simulations with 32-nm HP L/S show that substrate pits with below ~20 nm in depth would not be printed on
the wafer if they could be smoothed by ML process down to ~1 nm in depth on ML surface. Through the investigation of
inspectability for programmed pits, minimum pit sizes detected by KLA6xx, AIT, and M7360 depend on ML smoothing
performance. Furthermore, printability results for pit defects also correlate with smoothed pit sizes. AIT results for
patterned mask with 32-nm HP L/S represents that minimum printable size of pits could be ~28.3 nm of SEVD. In
addition, printability of pits became more printable as defocus moves to (-) directions. Consequently, printability of
phase defects strongly depends on their locations with respect to those of absorber patterns. This indicates that defect
compensation by pattern shift could be a key technique to realize zero printable phase defects in EUVL masks.
Phase-shifting EUVL masks applying thinner absorber are investigated to design optimum mask structure with less shadowing problems. Simulations using S-Litho show that H-V bias in Si capping structure is higher than that of Ru capping since the high n (= 0.999) of Si increases sensible absorber height. Phase differences obtained from the patterned masks using the EUV CSM are well-matched with the calculated values using the practical refractive index of absorber materials. Although the mask with 62.4-nm-thick absorber, among the in-house masks, shows the closest phase ΔΦ(= 176°) to the out-of-phase condition, higher NILS and contrast as well as lower H-V bias are obtained with 52.4-nm-thick absorber (ΔΦ = 151°) which has higher R/R0 ratio. MET results also show that lithography performances including MEEF, PW, and resist threshold (dose), are improved with thinner absorber structure. However, low OD in EUVL mask, especially in thinner absorber structure, results in light leakage from the neighboring exposure shots, and thus an appropriate light-shielding layer should be introduced.
Lifetime of EUVL masks which are intentionally contaminated with carbon is investigated by comparing Si and Ru
capping layer. Carbon deposition is observed not only on the multilayer, but also on the absorber sidewall of the mask.
Deposited carbon on the sidewall during EUV exposure gradually varies mask CD and also induces the changes in the
wafer printability and dose in the scanner. In addition, we compare the effects of carbon contamination between Si and
Ru capped blank. Ru capped blank shows longer mask mean time between cleaning (MTBC) than Si capped blank by 25% in our experiments.
GDSII is a data format of the circuit design file for producing semiconductor. GDSII is also used as a transfer format for
fabricating photo mask as well. As design rules are getting smaller and RET (Resolution Enhancement Technology) is
getting more complicated, the time of converting GDSII to a mask data format has been increased, which influences the
period of mask production. Photo mask shops all over the world are widely using computer clusters which are connected
through a network, that is, called distributed computing method, to reduce the converting time. Commonly computing
resource for conversion is assigned based on the input file size. However, the result of experiments showed that the
input file size was improper to predict the computing resource usage. In this paper, we propose the methodology of
artificial intelligence with considering the properties of GDSII file to handle circuit design files more efficiently. The
conversion time will be optimized by controlling the hardware resource for data conversion as long as the conversion
time is predictable through analyzing the design data. Neural networks are used to predict the conversion time for this
research. In this paper, the application of neural networks for the time prediction will be discussed and experimental
results will be shown with comparing to statistical model based approaches.
As the critical dimension (CD) becomes smaller, various resolution enhancement techniques (RET) are widely adopted. In developing sub-100nm devices, the complexity of optical proximity correction (OPC) is severely increased and applied OPC layers are expanded to non-critical layers. The transformation of designed pattern data by OPC operation causes complexity, which cause runtime overheads to following steps such as mask data preparation (MDP), and collapse of existing design hierarchy. Therefore, many mask shops exploit the distributed computing method in order to reduce the runtime of mask data preparation rather than exploit the design hierarchy. Distributed computing uses a cluster of computers that are connected to local network system. However, there are two things to limit the benefit of the distributing computing method in MDP. First, every sequential MDP job, which uses maximum number of available CPUs, is not efficient compared to parallel MDP job execution due to the input data characteristics. Second, the runtime enhancement over input cost is not sufficient enough since the scalability of fracturing tools is limited. In this paper, we will discuss optimum load balancing environment that is useful in increasing the uptime of distributed computing system by assigning appropriate number of CPUs for each input design data. We will also describe the distributed processing (DP) parameter optimization to obtain maximum throughput in MDP job processing.
As the design rule with wafer is tightening to sub-100nm, the specification of Mask CD uniformity is steeply tightened too. For instance, according to 2004 ITRS Roadmap updated, the specification of DRAM's CD uniformity requires less then 7nm on 80nm nodes in Yr. 2005. In order to satisfy that specification, it is important to analyze various factors such as e-beam machine error, heating effect, fogging effect, proximity effect, and process errors which cause CD non-uniformity in the mask.
In this paper, a simulation method will be introduced to calculate the local and global heating effect by applying DP(Distributed Processing). First, experiments were performed to see heating effects on mask CD uniformity. In case of the ZEP process with 50KeV exposure, the CD error caused by heating effect amounted to 45nm in worst case. Second, heating effect was simulated using DP. Recently, most simulators have been required high accuracy. However, it is inevitable to spend more calculation time. To improve that problem, DP has been adopted in many softwares. In this paper, MPI(Message Passing Interface) library was applied to simulate heating effect. Finally, the experiment and simulated results were compared. As a result, simulation results could explain the CD errors investigated on our experiment. In our experiment, 2D simulation is sufficient to expect CD errors caused by resist heating effect.
In this paper, the influence of dose modulation on CD trend by using electron beam exposure model has been investigated and simulated. To predict CD trend, we developed an analysis program, which shows the exposed energy profile and the corrected CD distribution in mask. First, it calculates the factor of fogging effect correction (Df) from pattern density distribution with the assumption that fogging effect depends on only pattern density. And then it calculates the modified dose for correcting both proximity and fogging effect. From dose distribution, the corrected CD is calculated analytically by using e-beam lithography model: see Figure 1. It can give a glance how the dose modulation method has an influence on the CD uniformity. Moreover, the result of global error correction such as side, radial error at the mask writing stage has been analyzed in this study.
In simulation of optical lithography it is well known that for high-NA the coupling between the vector components of the electromagnetic wave cannot be ignored and a vector diffraction theory should be employed to calculate aerial images. Commercial programs produce the same aerial image for scalar diffraction theory. When vector models are selected, they give the consistent images in latest versions. However formula of vector models give the different mathematical formula. To understand the origin of the difference, we compared the vector models adopted by Refs.
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