Dr. Céline Lapeyre Profile

Dr. Céline Lapeyre

Research Engineer at Commissariat à l'Energie Atomique

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Publications (23)

Proceedings Article | 27 April 2023 Poster + Paper

Enabling layer transfer and back-side power delivery network applications by wafer bonding and scanner correction optimizations

Richard van Haren, Suwen Li, Blandine Minghetti, Leon van Dijk, Klaas Brantjes, Frank Fournel, Gaëlle Mauguen, Ivanie Mendes, Céline Lapeyre, Marie-Line Pourteau, Michael May, Laurent Pain, Karine Abadie, Thomas Plach, Markus Wimplinger

Proceedings Volume 12496, 124962C (2023) https://doi.org/10.1117/12.2657422

KEYWORDS: Wafer bonding, Semiconducting wafers, Scanners, Silicon, Distortion, Optical alignment, Transistors, Oxides, Crystals, Etching

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Apart from the ever-continuing lateral scaling in the xy-plane to increase the transistor density, additional new concepts find their way to the semiconductor industry too. These concepts are based on making more use of the third dimension. One relatively simple idea would be to create a second layer of transistors to double the transistor density. However, the material requirements are high and the quality of the layer deposition by conventional Chemical Vapor Deposition (CVD) techniques is insufficient. Another application to free up real estate, enabling a smaller cell size and hence an increased transistor density, is to power-up the transistors from the backside. The power rails for logic devices are historically defined in the first Metal layer and consume quite some space. Bringing the power rails to the backside will free up space. However, access to the transistor layer from the backside of the wafer is far from trivial due to the presence of a 775-μm thick silicon substrate. The answer to the challenges mentioned above is wafer-to-wafer direct bonding. Although this technique is not new and already widely used in the semiconductor industry to manufacture CMOS Image Sensors (CIS), it currently finds its way to the high-end logic markets. In case of layer transfer, a crystalline silicon layer is created by bonding a Silicon-On- Insulator (SOI) wafer to the already existing device wafer. After the bonding step, the substrate of the SOI wafer will be removed leaving the crystalline silicon layer behind. Access to the transistor layer from the wafer backside can be enabled by wafer-to-wafer bonding as well. To this end, a completed device wafer will be bonded to an (un-patterned) carrier wafer. The substrate of the original device wafer will be removed, enabling access from the backside. Wafer-towafer bonding applications can only be enabled in case the induced wafer deformations are low or when they can easily be corrected during the subsequent exposures on the scanner. At CEA-Leti, a dedicated test vehicle process flow has been developed to characterize the wafer bonding-induced distortion fingerprints for both the layer transfer and the backside power delivery network applications. The wafer process flow has been simplified without losing the industry relevant on-product overlay challenges. Wafers have been created to enable an extremely dense characterization of the wafer bonding induced fingerprint. The methodology we applied enables us to isolate the wafer bonding induced distortion fingerprint, something that is difficult to do in a production environment. The Back-Side Power Delivery Network (BS-PDN) application is the most challenging one. The initial raw measured wafer distortion fingerprints are around 60 to 80-nm. These numbers can already be easily brought down by scanner corrections to ~15-nm (mean+3σ) without too much effort. However, these numbers are too large for the 2-nm technology node and beyond, and further improvement is required. The goal of this paper is to present the path forward to bring the bonding induced wafer distortion levels to 10-nm and below. We show the capability of the latest and greatest EVG bonding tool hardware and recipe settings available at the time of running the experiments in combination with the correction capability an ASML 0.33NA scanner.

Proceedings Article | 27 April 2023 Poster + Paper

Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay

Viorel Balan, Florent Michel, Ivanie Mendes, Celine Lapeyre, Lionel Vignoud, Ronald Otten, Orion Mouraille, Leon van Dijk, Blandine Minghetti, Jerome Depre, Richard van Haren

Proceedings Volume 12496, 1249633 (2023) https://doi.org/10.1117/12.2658296

KEYWORDS: Annealing, Semiconducting wafers, Metrology, Distortion, Overlay metrology, Deformation, Chemical mechanical planarization, Silicon, Optical interferometry, Manufacturing

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Proceedings Article | 20 March 2020 Paper

Stitched overlay evaluation and improvement for large field applications

Michael May, Blandine Minghetti, Jérome Dépré, Yoann Blancquaert, Pui Lam, Céline Lapeyre, Joungchel Lee

Proceedings Volume 11325, 113251L (2020) https://doi.org/10.1117/12.2552012

KEYWORDS: Overlay metrology, Metrology, Scanners, Critical dimension metrology

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Reducing the overlay error between stacked layers is key to enabling higher pattern density and thus moving towards high performance and more cost effective devices. However, as for specific applications like macrochips with photonic interconnects and high-resolution image sensor flat panels with advance polarizers, customers require product field sizes that are larger than the maximum field size available on scanners. Those large fields are obtained by stitching together multiple standard fields. The overlay performances between two adjacent dies are as aggressive as what is usually required between two stacked layers. For this application, the well-established polynomial overlay model is not suitable as the displacement is measured relatively and the metrology sampling in the field is such that some high order nonlinear (K) terms cannot be modeled independently. Furthermore, a perfect grid is needed in mix and match production. The intrafield correction capability of the exposure tool is not the same for each process steps. For example, no intrinsic K13 can be printed for a mix and match process flow that includes an Extreme Ultra-Violet (EUV) litho step. In addition, some KrF scanners with fewer lens manipulators cannot correct for K9. Measuring the stitching and correcting it at the first layer will prevent printing K terms that are not correctable later in the process. In this paper, the need to characterize and control single-layer overlay among different pattern placement mechanisms intrinsic to the scanner was studied: optical aberrations, field-to-field position, mask placement and registration. An ASML set-up BP-XY-V3 reticle was used to generate a large experimental dataset to validate stitching models supported by Overlay Optimizer (OVO). Overlay measurements were done Resist-in-Resist using new YieldStar (YS) interlaced stitching Diffraction Based Overlay (μDBO) targets that were designed and validated. This paper will present on product metrology results of a scatterometry-based platform showing production results with focus not only on precision and on accuracy, but also assessing target performance and target-to-target delta without process influence. A high order stitching model was developed and verified on a Multi-Product Reticle for a large device application. Trench width control at the field intersection was studied then optimized with proximity correction to ensure a perfect field-to-field junction.

Proceedings Article | 19 March 2018 Presentation

Inorganic guiding template implementation for DSA contact hole shrink process (Conference Presentation)

Ahmed Gharbi, Florian DELACHAT, Patricia Pimenta-Barros, Gaëlle Chamiot-Maitral, Maxime Argoud, Celine Lapeyre, Laurent Pain, Christophe Navarro, Célia Nicolet, Ian Cayrefourcq, Raluca Tiron

Proceedings Volume 10584, 105840D (2018) https://doi.org/10.1117/12.2297422

KEYWORDS: Directed self assembly, Optical lithography, Critical dimension metrology, Silicon, Oxides, Semiconducting wafers, Semiconductors, Materials processing, Photomasks, Photoresist processing

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Proceedings Article | 10 April 2017 Presentation + Paper

Nanoimprint, DSA, and multi-beam lithography: patterning technologies with new integration challenges

S. Landis, H. Teyssedre, G. Claveau, I. Servin, F. Delachat, M. L. Pourteau, A. Gharbi, P. Pimenta Barros, R. Tiron, L. Nouri, N. Possemé, M. May, P. Brianceau, S. Barnola, Y. Blancquaert, J. Pradelles, P. Essomba, A. Bernadac, B. Dal'zotto, S. Bos, M. Argoud, G. Chamiot-Maitral, A. Sarrazin, C. Tallaron, C. Lapeyre, L. Pain

Proceedings Volume 10149, 101490K (2017) https://doi.org/10.1117/12.2259966

KEYWORDS: Directed self assembly, Lithography, Line width roughness, Nanoimprint lithography, Semiconducting wafers, Etching, Electron beam lithography, System on a chip, Critical dimension metrology, Photoresist processing

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Proceedings Article | 21 March 2017 Paper

Advanced surface affinity control for DSA contact hole shrink applications

Florian Delachat, Ahmed Gharbi, Patricia Pimenta Barros, Maxime Argoud, Céline Lapeyre, Sandra Bos, Jérôme Hazart, Laurent Pain, Cédric Monget, Xavier Chevalier, Célia Nicolet, Christophe Navarro, Ian Cayrefourcq, Raluca Tiron

Proceedings Volume 10144, 101440O (2017) https://doi.org/10.1117/12.2258043

KEYWORDS: Directed self assembly, Lithography, Immersion lithography, Polymers, Semiconducting wafers, Polymethylmethacrylate, Scanning electron microscopy, Inspection, Image processing, Picosecond phenomena

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SPIE Journal Paper | 18 October 2016

Process highlights to enhance directed self-assembly contact patterning performances

Ahmed Gharbi, Raluca Tiron, Maxime Argoud, Gaëlle Chamiot-Maitral, Antoine Fouquet, Céline Lapeyre, Patricia Pimenta-Barros, Florian Delachat, Sandra Bos, Shayma Bouanani, Xavier Chevalier, Célia Nicolet, Christophe Navarro, Ian Cayrefourcq, Laurent Pain

JM3, Vol. 15, Issue 04, 043503, (October 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.4.043503

KEYWORDS: Directed self assembly, Optical lithography, Annealing, Picosecond phenomena, Critical dimension metrology, Scanning electron microscopy, Materials processing, Semiconducting wafers, Lithography, Molecular self-assembly

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SPIE Journal Paper | 27 April 2016

Placement error in directed self-assembly of block copolymers for contact hole application

Shayma Bouanani, Raluca Tiron, Sandra Bos, Ahmed Gharbi, Patricia Pimenta-Barros, Jérôme Hazart, Frédéric Robert, Céline Lapeyre, Alain Ostrovsky, Cédric Monget

JM3, Vol. 15, Issue 02, 021407, (April 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.2.021407

KEYWORDS: Directed self assembly, Critical dimension metrology, Polymethylmethacrylate, Smoothing, Image processing, Materials processing, Edge detection, Polymers, Error analysis, Metrology

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Proceedings Article | 1 April 2016 Paper

Investigation of coat-develop track system for placement error of contact hole shrink process

Masahiko Harumoto, Harold Stokes, Yuji Tanaka, Koji Kaneyama, Charles Pieczulewski, Masaya Asai, Isabelle Servin, Maxime Argoud, Ahmed Gharbi, Celine Lapeyre, Raluca Tiron, Cedric Monget

Proceedings Volume 9777, 97770O (2016) https://doi.org/10.1117/12.2219925

KEYWORDS: Lithography, Semiconducting wafers, Directed self assembly, Image processing, Scanning electron microscopy, Etching, Immersion lithography, Optical lithography, Annealing, Distance measurement

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Proceedings Article | 22 March 2016 Paper

Process highlights to enhance DSA contact patterning performances

A. Gharbi, R. Tiron, M. Argoud, G. Chamiot-Maitral, A. Fouquet, C. Lapeyre, P. Pimenta Barros, A. Sarrazin, I. Servin, F. Delachat, S. Bos, S. Bérard-Bergery, J. Hazart, X. Chevalier, C. Nicolet, C. Navarro, I. Cayrefourcq, S. Bouanani, C. Monget

Proceedings Volume 9777, 97770T (2016) https://doi.org/10.1117/12.2219210

KEYWORDS: Directed self assembly, Optical lithography, Inspection, Lithography, Etching, Semiconducting wafers, Scanning electron microscopy, Defect detection, Critical dimension metrology, Materials processing, Photomasks, Picosecond phenomena, Annealing, Molecular self-assembly, Image processing

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SPIE Journal Paper | 10 April 2015

Patterning critical dimension control for advanced logic nodes

Bertrand Le-Gratiet, Jean De-Caunes, Maxime Gatefait, Auguste Lam, Alain Ostrovsky, Jonathan Planchot, Vincent Farys, Julien Ducoté, Marc Mikolajczak, Vincent Morin, Nicolas Chojnowski, Frank Sundermann, Alice Pelletier, Regis Bouyssou, Cedric Monget, Jean-Damien Chapon, Bastien Orlando, Laurene Babaud, Céline Lapeyre, Emek Yesilada, Anna Szucs, Jean-Christophe Michel, Latifa Desvoivres, Onintza Ros Bengoechea, Pascal Gouraud

JM3, Vol. 14, Issue 02, 021103, (April 2015) https://doi.org/10.1117/12.10.1117/1.JMM.14.2.021103

KEYWORDS: Semiconducting wafers, Optical lithography, Critical dimension metrology, Process control, Photomasks, Etching, Logic, Metrology, Lithography, Optical proximity correction

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Proceedings Article | 19 March 2015 Paper

Template affinity role in CH shrink by DSA planarization

R. Tiron, A. Gharbi, P. Pimenta Barros, S. Bouanani, C. Lapeyre, S. Bos, A. Fouquet, J. Hazart, X. Chevalier, M. Argoud, G. Chamiot-Maitral, S. Barnola, C. Monget, V. Farys, S. Berard-Bergery, L. Perraud, C. Navarro, C. Nicolet, G. Hadziioannou, G. Fleury

Proceedings Volume 9423, 942317 (2015) https://doi.org/10.1117/12.2085819

KEYWORDS: Polymethylmethacrylate, Lithography, Semiconducting wafers, Picosecond phenomena, Etching, Error analysis, Optical lithography, Line edge roughness, Image processing, Directed self assembly

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Density multiplication and contact shrinkage of patterned templates by directed self-assembly (DSA) of block copolymers (BCP) stands out as a promising alternative to overcome the limitations of conventional lithography. The main goal of this paper is to investigate the potential of DSA to address contact and via levels patterning with high resolution by performing either CD shrink or contact multiplication. Different DSA processes are benchmarked based on several success criteria such as: CD control, defectivity (missing holes) as well as placement control. More specifically, the methodology employed to measure DSA contact overlay and the impact of process parameters on placement error control is detailed. Using the 300mm pilot line available in LETI and Arkema’s materials, our approach is based on the graphoepitaxy of PS-b-PMMA block copolymers. Our integration scheme, depicted in figure 1, is based on BCP self-assembly inside organic hard mask guiding patterns obtained using 193i nm lithography. The process is monitored at different steps: the generation of guiding patterns, the directed self-assembly of block copolymers and PMMA removal, and finally the transfer of PS patterns into the metallic under layer by plasma etching. Furthermore, several process flows are investigated, either by tuning different material related parameters such as the block copolymer intrinsic period or the interaction with the guiding pattern surface (sidewall and bottom-side affinity). The final lithographic performances are finely optimized as a function of the self-assembly process parameters such as the film thickness and bake (temperature and time). Finally, DSA performances as a function of guiding patterns density are investigated. Thus, for the best integration approach, defect-free isolated and dense patterns for both contact shrink and multiplication (doubling and more) have been achieved on the same processed wafer. These results show that contact hole shrink and multiplication approach using DSA is well compatible with the conventional integration used for CMOS technology.

Proceedings Article | 17 March 2015 Paper

DSA planarization approach to solve pattern density issue

P. Pimenta Barros, A. Gharbi, Aurélien Sarrazin, R. Tiron, N. Posseme, S. Barnola, S. Bos, C. Tallaron, G. Claveau, X. Chevalier, M. Argoud, Isabelle Servin, C. Navarro, Célia Nicolet, C. Lapeyre, C. Monget

Proceedings Volume 9428, 94280D (2015) https://doi.org/10.1117/12.2086810

KEYWORDS: Polymethylmethacrylate, Etching, Critical dimension metrology, Picosecond phenomena, Semiconducting wafers, Chemistry, Scanning electron microscopy, Carbon monoxide, Dry etching, Directed self assembly

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Proceedings Article | 17 October 2014 Paper

How holistic process control translates into high mix logic fab APC?

B. Le-Gratiet, M. Gatefait, J. Ducotè, J. Decaunes, A. Lam, B. Beraud, M. Mikolajczak, A. Pelletier, B. Orlando, F. Sundermann, A. Ostrovsky, C. Lapeyre

Proceedings Volume 9231, 92310V (2014) https://doi.org/10.1117/12.2064795

KEYWORDS: Semiconducting wafers, Photomasks, Process control, Scanners, Metrology, Etching, Databases, Logic, Data modeling, Control systems

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Proceedings Article | 28 March 2014 Paper

Etch challenges for DSA implementation in CMOS via patterning

P. Pimenta Barros, S. Barnola, A. Gharbi, M. Argoud, I. Servin, R. Tiron, X. Chevalier, C. Navarro, C. Nicolet, C. Lapeyre, C. Monget, E. Martinez

Proceedings Volume 9054, 90540G (2014) https://doi.org/10.1117/12.2046267

KEYWORDS: Etching, Polymethylmethacrylate, Picosecond phenomena, Plasma, Chemistry, Optical lithography, Argon, Dry etching, Dielectrics, Directed self assembly

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Proceedings Article | 21 March 2012 Paper

Sub-20nm hybrid lithography using optical, pitch-division, and e-beam

J. Belledent, M. Smayling, J. Pradelles, P. Pimenta-Barros, S. Barnola, L. Mage, B. Icard, C. Lapeyre, S. Soulan, L. Pain

Proceedings Volume 8323, 83230F (2012) https://doi.org/10.1117/12.916486

KEYWORDS: Electron beam lithography, Photomasks, Lithography, Optical lithography, Logic, Optics manufacturing, Semiconducting wafers, Double patterning technology, Neodymium, Scanning electron microscopy

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A roadmap extending far beyond the current 22nm CMOS node has been presented several times. [1] This roadmap includes the use of a highly regular layout style which can be decomposed into "lines and cuts."[2] The "lines" can be done with existing optical immersion lithography and pitch division with self-aligned spacers.[3] The "cuts" can be done with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write ebeam.[ 4] The choice for "cuts" will be driven by the availability of cost-effective, manufacturing-ready equipment and infrastructure. Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography. With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the "lines and cuts" approach can extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography. For practical reasons, E-Beam lithography is used as well to expose the "mandrel" patterns that support the spacers. However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and applying the spacer technique twice to divide the pitch by 3 or 4. The Metal-1 "cut" pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Since the final conductor is defined by a Damascene process, the "cut" patterns become islands of resist blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer with reasonable overlay margin. The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a scaling path far into the future.

Proceedings Article | 23 March 2011 Paper

Scanner alignment performance for double patterning

L. Lattard, M. McCallum, R. Morton, C. Lapeyre, K. Makino, A. Tokui, N. Takahashi, T. Fujiwara

Proceedings Volume 7973, 79730I (2011) https://doi.org/10.1117/12.878953

KEYWORDS: Optical alignment, Double patterning technology, Scanners, Lithography, Overlay metrology, Optical lithography, Critical dimension metrology, Semiconducting wafers, Double positive medium, Etching

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Proceedings Article | 27 May 2009 Paper

Mask contribution on CD and OVL errors budgets for double patterning lithography

I. Servin, C. Lapeyre, S. Barnola, B. Connolly, R. Ploss, K. Nakagawa, P. Buck, M. McCallum

Proceedings Volume 7470, 747009 (2009) https://doi.org/10.1117/12.835171

KEYWORDS: Photomasks, Semiconducting wafers, Critical dimension metrology, Reticles, Double patterning technology, Pellicles, Lithography, Image registration, Optical alignment, Scanners

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Proceedings Article | 16 March 2009 Paper

Impact of CD and overlay errors on double-patterning processes

Céline Lapeyre, Sébastien Barnola, Isabelle Servin, Stéphanie Gaugirana, Vincent Salvetat, Nobutaka Magome, Andrew Hazelton, Martin McCallum

Proceedings Volume 7274, 72740W (2009) https://doi.org/10.1117/12.814165

KEYWORDS: Double patterning technology, Etching, Semiconducting wafers, Lithography, Photomasks, Image processing, Photoresist processing, Reticles, Line width roughness, Overlay metrology

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Proceedings Article | 16 March 2009 Paper

Achieving overlay budgets for double patterning

Andrew Hazelton, Nobutaka Magome, Shinji Wakamoto, Akira Tokui, Céline Lapeyre, Sébastien Barnola, Guillaume Jullien, Vincent Salvetat

Proceedings Volume 7274, 72740X (2009) https://doi.org/10.1117/12.813599

KEYWORDS: Double patterning technology, Optical alignment, Semiconducting wafers, Optical lithography, Distortion, Etching, Overlay metrology, Lithography, Reticles, Logic

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Proceedings Article | 16 March 2009 Paper

Integration of dry etching steps for double patterning and spacer patterning processes

S. Barnola, C. Lapeyre, I. Servin, C. Arvet, P. Maury, L. Mage

Proceedings Volume 7274, 72741X (2009) https://doi.org/10.1117/12.814856

KEYWORDS: Etching, Carbon, Double patterning technology, Photomasks, Optical lithography, Chemistry, Lithography, Critical dimension metrology, Plasma, Scanning electron microscopy

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SPIE Journal Paper | 1 January 2009

Double-patterning requirements for optical lithography and prospects for optical extension without double patterning

Andrew Hazelton, Shinji Wakamoto, Shigeru Hirukawa, Martin McCallum, Nobutaka Magome, Jun Ishikawa, Céline Lapeyre, Isabelle Guilmeau, Sébastien Barnola, Stéphanie Gaugiran

JM3, Vol. 8, Issue 01, 011003, (January 2009) https://doi.org/10.1117/12.10.1117/1.3023077

KEYWORDS: Double patterning technology, Photomasks, Etching, Reticles, Lithography, Optical lithography, Semiconducting wafers, Image processing, Photoresist processing, Deposition processes

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Proceedings Article | 7 March 2008 Paper

Double patterning requirements for optical lithography and prospects for optical extension without double patterning

Andrew Hazelton, Shinji Wakamoto, Shigeru Hirukawa, Martin McCallum, Nobutaka Magome, Jun Ishikawa, Céline Lapeyre, Isabelle Guilmeau, Sébastien Barnola, Stéphanie Gaugiran

Proceedings Volume 6924, 69240R (2008) https://doi.org/10.1117/12.771914

KEYWORDS: Double patterning technology, Photomasks, Etching, Reticles, Semiconducting wafers, Lithography, Image processing, Photoresist processing, Optical lithography, Deposition processes

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