In order to minimize wafer loss and increase productivity, it is important to predict the wafer yield drop caused by defects in early manufacturing stage. In conventional yield prediction method, the chip failure was manually checked using images sampled by defect inspection. However, it is insufficient to predict yield accurately since the prediction was performed with only a few sampled defect images. Furthermore, the kill-ratio per defect was not estimated properly because the electrical properties were not considered in predicting a failure such as short or open. In this paper, we propose a new yield prediction method using defect and layout information with the following two characteristics. We tried to overcome the existing sampling limitations by using the defect inspection raw data that contains the coordinates and size information of all defects. In addition, we matched the electrical signal information of the layout pattern with silicon directly and then calculated the kill ratio per defect. The kill ratio per defect has doubled from 30% to 70% applied to sub-20nm Emerging memory devices. And we have confirmed that the yield prediction gap, which is the difference between the predicted yield and the actual yield, decreases from 31% to 8%. It is expected to reduce wafer loss about 10% in Emerging memory devices and same improvement will occur in other products such as DRAM, FLASH, and LOGIC devices by applying this sophisticated methodology.
As the technology node shrinks, the systematic defects such as the missing and extra pattern are generated in the process of cell patterning. The defect such as the extra and missing pattern can lead to a critical failure on device. Subsequently, the systematic defect in the UBE could be an etch-gas path on proceeding the etch process and cause the quality degradation of device. In this paper, we propose an automated system to inspect the systematic defect in the cell array with the scanning electron microscope (SEM) image and the physical design. The method consists of conversion, matching, and detection. In the conversion method, the SEM image is converted into the layout using image processing such as noise reduction, segmentation and contour tracing. In the following matching method, gradient descent optimization is used to match the coordinate of layout converted from the SEM image with the coordinate of physical design. In the final detection method, the defect is detected by inspecting the patterns of two layouts. On the test of 2,500 data, we confirmed that the accuracy improved from 97% to 100% as a result of comparing the engineer's visual inspection method with the proposed method. In addition, the turnaround time (TAT) is improved by approximately 40 times. The proposed system is currently applied to DRAM products and used for the field of design for manufacturing (DFM) and manufacturing process.
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