This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently
proposed. This interconnect system uses point-to-point free-space optical links to construct an all-to-all intra-chip communication
network. Unlike other electrical and waveguide-based optical interconnect systems, FSOI exhibits low latency,
high energy efficiency, and large bandwidth density with little degradation for long distance transmission, and hence can
significantly improve the performance of future many-core chips. A 1x1-cm2 chip prototype is fabricated on a germanium
substrate with integrated photodetectors. A commercial 850-nm GaAs vertical-cavity-surface-emitting-laser (VCSEL) and
fabricated fused silica micro-lenses are 3-D integrated on top of the germanium substrate. At a 1.4-cm distance, the measured
optical transmission loss is 5 dB and crosstalk is less than -20 dB. The electrical-to-electrical bandwidth is 3.3 GHz,
limited by the VCSEL.
KEYWORDS: Sensors, Infrared sensors, System on a chip, Infrared imaging, Analog electronics, 3D image processing, Digital signal processing, Silicon, Acoustics, 3D modeling
This paper describes a new concept for ultra-small, ultra-compact, unattended multi-phenomenological sensor systems for rapid deployment, with integrated classification-and-decision-information extraction capability from a sensed environment. We discuss a unique approach, namely a 3-D Heterogeneous System on a Chip (HSoC) in order to achieve a minimum 10X reduction in weight, volume, and power and a 10X or greater increase in capability and reliability -- over the alternative planar approaches. These gains will accrue from (a) the avoidance of long on-chip interconnects and chip-to-chip bonding wires, and (b) the cohabitation of sensors, preprocessing analog circuitry, digital logic and signal processing, and RF devices in the same compact volume. A specific scenario is discussed in detail wherein a set of four types of sensors, namely an array of acoustic and seismic sensors, an active pixel sensor array, and an uncooled IR imaging array are placed on a common sensor plane. The other planes include an analog plane consisting of transductors and A/D converters. The digital processing planes provide the necessary processing and intelligence capability. The remaining planes provide for wireless communications/networking capability. When appropriate, this processing and decision-making will be accomplished on a collaborative basis among the distributed sensor nodes through a wireless network.
Conference Committee Involvement (4)
VLSI Circuits and Systems
18 April 2011 | Prague, Czech Republic
VLSI Circuits and Systems
4 May 2009 | Dresden, Germany
VLSI Circuits and Systems
2 May 2007 | Maspalomas, Gran Canaria, Spain
VLSI Circuits and Systems
19 May 2003 | Maspalomas, Gran Canaria, Canary Islands, Spain
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