We evaluated the chromium-shielding attenuated phase shift mask (Cr-shield att-PSM) for the fabrication of fine hole patterns in 157-nm lithography. The transmittance of the phase shifter was set at 5% to achieve the best performance for 70- to 90-nm-diameter holes. Simulation and experimental results indicated that the optimum distance a between the pattern edge and the Cr-shield edge changed depending on the size and pitch of the holes. The optimum distance a for sub-70-nm-diameter holes was zero, which meant the binary mask gives the best depth of focus. In the case of 80-nm-diameter holes, the conventional att-PSM proved to be the best option for 1:1 hole patterns. For 1:2 hole patterns, the optimized distance a was 60 to 70 nm. For isolated hole patterns, the optimum distance a was 45 nm. After optimizing distance a, we confirmed the side-lobe control capability of the Cr-shield att-PSM through exposure experiments. The elimination of side-lobes greatly improved the resolution. Furthermore, we found that the mask linearity was improved through use of a Cr-shield att-PSM.
The potential for extending the numerical aperture (NA) in order to develop devices beyond the 45-nm node has been investigated using a 157-nm microstepper exposure tool at 0.90NA (third generation) and verifying the resolution limit of several different resolution enhancement techniques. It was observed that with 157-nm lithography at 0.90NA a 60-nm line and space (L/S) and a 50-nm isolated line could be formed by using an attenuated phase shifting mask (Att-PSM), and that a 50-nm L/S and a 35-nm isolated line could be formed by using an alternating phase shifting mask (Alt-PSM). The influence of the flare for the same pattern sizes was more severe for the L/S pattern rather than isolated line. However, it was the most difficult to image an isolated line with an Att-PSM, which was limited with a tolerance to the flare of less than 1%. Furthermore, the requirement of more than 0.93 for lens NA was confirmed in order to fabricate half pitch 65-nm node device with Att-PSM and half pitch 45-nm node device with Alt-PSM. Results obtained in the pattern formation of 45-nm node with an Alt-PSM confirmed that a 35-nm line could be formed down to 140-nm pitch, a 40-nm line could be formed down to 135-nm pitch, and a 45-nm line could be formed down to 100-nm pitch. It has been demonstrated that 157-nm lithography could find application to half-pitch 65-nm and 45-nm node devices.
The TaSiOx attenuated phase-shifting mask (Att-PSM) has strong potential for durability against laser irradiation and good lithographic performance in 157 nm lithography. However, the resist resolution limit and depth of focus (DOF) are deteriorated by side-lobe patterns generated near the contact hole. This is because the side-lobe intensity generated near the light-transmitting region becomes larger in sub 100 nm contact holes. To minimize the effect of side-lobes and improve lithographic performance, we evaluated an Att-PSM with a chrome light-shielding layer and optimized the transmittance of its attenuated phase-shifting film. In an optical simulation, we investigated the effect of the side-lobe intensity on the resist region (i.e., a reduction in resist thickness). The light-shielding film was placed on the attenuated phase-shifting film to prevent the side-lobe pattern, and its effect on the imaginary resist pattern was simulated. We found that the distance between the patterning edge of the hole and that of the light-shielding region must be greater than 90 nm to fabricate a 100 nm isolated hole without side-lobe patterns. The side-lobe intensity could be controlled using the chrome-shielding-type Att-PSM, and the lithographic performance (such as resolution limit and DOF) was enhanced.
A phase-shifting mask (PSM) is one of the most effective resolution enhancement technologies to improve the resolution limit and process margins such as exposure latitude (EL) and depth of focus (DOF). The attenuated phase-shifting mask (Att-PSM) is the most practical PSM, because it has a simple structure and can be easily fabricated. However, it is very difficult to evaluate the impact of using Att-PSMs on the resolution limit and process margin, under the condition of both a shorter wavelength and higher numerical aperture (NA). The reason is that the resolution improvement of the Att-PSM is very small under the above condition. In this study, we investigate the impact of using the Att-PSM instead of a binary mask under the conditions of shorter wavelength (157-nm) and higher-NA (0.85-NA). We evaluated the resolution limit by both aerial image simulation and exposure experiment. The aerial image simulation confirmed that the resolution improvement in the line and space pattern that can be expected from an Att-PSM of 5% transmittance diminished by decreasing wavelength and increasing NA. In particular, when a wavelength of 157-nm and an NA of 0.85 are used, we obtained a 6% resolution improvement compared to the binary mask. In the exposure experiment, we obtained an 11% resolution improvement when using a TaSiOx-type Att-PSM of 5.7% transmittance. From these results, we found that the Att-PSM can be used to fabricate smaller size features even shorter wavelength of 157-nm and the higher NA of 0.85.
We evaluated the requirements for 65-nm SRAM gate fabrication using attenuated phase shifting masks (att-PSM). Off-axis illumination (OAI) and att-PSM, together with optical proximity correction (OPC) were used as resolution enhancement techniques (RETs) for ultimate resolution. It was shown that the photolithographic parameters of the transmittance of the att-PSM and the illumination conditions for optimum conditions were a transmittance of between 15 and 20% and 3/4 annular illumination. The exposure latitude was simulated to be more than 10.9% at 300-nm defocus for a critical dimension (CD) specification of 10%. It has been demonstrated that a 65-nm SRAM-gate, with a line and space (L/S) ratio limited to 1:2 at the minimum pitch, could be fabricated with sufficient depth of focus (DOF). The pattern transfer was accomplished with a bi-layer process, in which the reactive ion etching (RIE) selectivity between a silicon-containing resist and an organic film is very high. This bi-layer process enabled the application of a very thin resist layer. The conditions described in this paper proved successful for the fabrication of a 65-nm SRAM gate with a good pattern profile despite the resist thickness of less than 120nm.
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