Mr. Foster Huang Profile

Foster Huang

at Nanya Technology Corp

SPIE Involvement:

Author

Publications (7)

Proceedings Article | 10 April 2024 Poster + Paper

NZO reduction via small pitch imaging-based overlay targets

Cheng-Ta Cheng, Hong Ching, Foster Huang, Zephyr Liu, Dor Yehuda, Michael Har-Zvi, Chris Hsieh, Penny Lin, York Yang

Proceedings Volume 12955, 1295530 (2024) https://doi.org/10.1117/12.3010703

KEYWORDS: Metrology, Overlay metrology, Inspection, Design, Optical parametric oscillators, Design rules, Semiconducting wafers, Scanners, Etching, Diffractive optical elements

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Proceedings Article | 10 April 2024 Presentation + Paper

Evaluating the probabilistic process window for use in high volume manufacturing

Tsu-Wen Huang, Ken-Huan Ho, Cheng-Wei Yang, Yao-Hsiung Kung, Lin-Chin Su, Chris Mack

Proceedings Volume 12955, 129551A (2024) https://doi.org/10.1117/12.3011706

KEYWORDS: Line width roughness, Metrology, Critical dimension metrology, Stochastic processes, Semiconducting wafers, Defect inspection, Measurement uncertainty, Calibration, High volume manufacturing

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Proceedings Article | 10 April 2024 Poster + Paper

Enable in-die overlay measurement on DRAM storage node by line scan self-calibration method

Fang-Jyun (June) Yeh, Shang-Hong (Sam) Tsai, Cheng An Lin, Cheng Wei Yang, Kai Ping Chan, Cheng Ta Cheng, Foster Huang, Henry Chen, Cheng-Hang Yang, Yun-Ju (York) Yang, Peter Paquet, Houssam Chouaib, Zhengquan Tan

Proceedings Volume 12955, 129552D (2024) https://doi.org/10.1117/12.3009960

KEYWORDS: Overlay metrology, Mueller matrices, Machine learning, Education and training, Semiconducting wafers, Calibration, Transmission electron microscopy, Metrology, Chemical elements, Algorithm development

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Proceedings Article | 26 May 2022 Presentation + Paper

Ultra-high throughput e-beam inspection for DRAM high aspect ratio storage node defect detection

Tsewen Huang, Shueming Chen, Kevin Hsiao, Steve Lin, Ray Fei, Yufei Duan, Kevin Gao, Luke Lin, Selena Chen

Proceedings Volume 12053, 120530J (2022) https://doi.org/10.1117/12.2617685

KEYWORDS: Defect detection, Inspection, Transmission electron microscopy, Signal detection, Sensors, Semiconducting wafers, Scanning electron microscopy, Defect inspection, Data storage

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Proceedings Article | 22 February 2021 Poster + Presentation + Paper

Investigation and optimization of STI dry-etch induced overlay through patterned wafer geometry tool

Tsu-Wen Huang, Ying-Cheng Chuang, Hsuan-Jui Huang, Chung-Chang Liu, Hsiao-Lun Chu, Sheng-Yu Chen, Ming-Ju Li, Jun-Eu Tang, Chiou-Shoei Chee, Choon-Wai Chang, Tung-Ying Lee

Proceedings Volume 11611, 1161139 (2021) https://doi.org/10.1117/12.2584589

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Proceedings Article | 20 October 2020 Presentation + Paper

Patterning solutions for NTD contact hole levels in advanced DRAM nodes

Michael Green, Tsu-Wen Huang, Mohamed Ramadan, Hung-Chang Szu, Yeu Dong Gau, Chih-Ying Tsai, Young Ham, Chun-Cheng Liao, Lucien Bouchard, Eric Huang, Wei-Cheng Shiu, Chris Progler

Proceedings Volume 11518, 115180N (2020) https://doi.org/10.1117/12.2574713

KEYWORDS: Photomasks, Optical lithography, Semiconducting wafers, Lithography, Optical proximity correction, Immersion lithography, 193nm lithography, Critical dimension metrology

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Proceedings Article | 26 March 2019 Paper

Overlay run-to-run control based on device structure measured overlay in DRAM HVM

Hsiao Lun Chu, Foster Huang, Steven Tottewitz, Boris Habets, Patrick Lomtscher, Hsiao-Lin Hsu, Afu Chiu, Rex Liu

Proceedings Volume 10959, 109592P (2019) https://doi.org/10.1117/12.2515203

KEYWORDS: Overlay metrology, Etching, Device simulation, Feedback control, Lithography, Measurement devices, Semiconducting wafers, Control systems, High volume manufacturing, Inspection

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In leading edge lithography, overlay is usually controlled by feedback based on measurements on overlay targets, which are located between the dies. These measurements are done directly after developing the wafer. However, it is well-known that the measurement on the overlay marks does not always represent the actual device overlay correctly. This can be due to different factors, including mask writing errors, target-to-device differences and non-litho processing effects, for instance by the etch process.¹

In order to verify these differences, overlay measurements are regularly done after the final etch process. These post-etch overlay measurements can be performed by using the same overlay targets used in post-litho overlay measurement or other targets. Alternatively, they can be in-device measurements using electron beam measurement tools (for instance CD-SEM). The difference is calculated between the standard post-litho measurement and the post-etch measurement. The calculation result is known as litho-etch overlay bias.

This study focuses on the feasibility of post-etch overlay measurement run-to-run (R2R) feedback instead of post-lithography R2R feedback correction. It is known that the post-litho processes have strong non-linear influences on the in-device overlay signature and, hence, on the final overlay budget. A post-etch based R2R correction is able to mitigate such influences.²

This paper addresses several questions and challenges related to post-etch overlay measurement with respect to R2R feedback control. The behavior of the overlay targets in the scribe-line is compared to the overlay behavior of device structures. The influence of different measurement methodologies (optical image-based overlay vs. electron microscope overlay measurement) was evaluated. Scribe-line standard overlay targets will be measured with electron microscope measurement. In addition, the influence of the intra-field location of the targets on device-to-target shifts was evaluated.

Showing 5 of 7 publications

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