The explosive volume growth of deep-learning (DL) applications has triggered an era in computing, with neuromorphic photonic platforms promising to merge ultra-high speed and energy efficiency credentials with the brain-inspired computing primitives. The transfer of deep neural networks (DNNs) onto silicon photonic (SiPho) architectures requires, however, an analog computing engine that can perform tiled matrix multiplication (TMM) at line rate to support DL applications with a large number of trainable parameters, similar to the approach followed by state-of-the-art electronic graphics processing units. Herein, we demonstrate an analog SiPho computing engine that relies on a coherent architecture and can perform optical TMM at the record-high speed of 50 GHz. Its potential to support DL applications, where the number of trainable parameters exceeds the available hardware dimensions, is highlighted through a photonic DNN that can reliably detect distributed denial-of-service attacks within a data center with a Cohen’s kappa score-based accuracy of 0.636.
The emergence of demanding machine learning and AI workloads in modern computational systems and Data Centers (DC) has fueled a drive towards custom hardware, designed to accelerate Multiply-Accumulate (MAC) operations. In this context, neuromorphic photonics have recently attracted attention as a promising technological candidate, that can transfer photonics low-power, high bandwidth credentials in neuromorphic hardware implementations. However, the deployment of such systems necessitates progress in both the underlying constituent building blocks as well as the development of deep learning training models that can take into account the physical properties of the employed photonic components and compensate for their non-ideal performance. Herein, we present an overview of our progress in photonic neuromorphic computing based on coherent layouts, that exploits the phase of the light traversing the photonic circuitry both for sign representation and matrix manipulation. Our approach breaks-through the direct trade-off of insertion loss and modulation bandwidth of State-Of-The-Art coherent architectures and allows high-speed operation in reasonable energy envelopes. We present a silicon-integrated coherent linear neuron (COLN) that relies on electro-absorption modulators (EAM) both for its on-chip data generation and weighting, demonstrating a record-high 32 GMAC/sec/axon compute linerate and an experimentally obtained accuracy of 95.91% in the MNIST classification task. Moreover, we present our progress on component specific neuromorphic circuitry training, considering both the photonic link thermal noise and its channel response. Finally, we present our roadmap on scaling our architecture using a novel optical crossbar design towards a 32×32 layout that can offer >;32 GMAC/sec/axon computational power in ~0.09 pJ/MAC.
Neuromorphic computing has emerged as a highly-promising compute alternative, migrating from von-Neuman architectures towards mimicking the human brain for sustaining computational power increases within a reduced power consumption envelope. Electronic neuromorphic chips like IBM’s TrueNorth, Intel’s Loihi and Mythic’s AI platform reveal a tremendous performance improvement in terms of computational speed and density; at the same time, neuromorphic photonic layouts are constantly gaining ground in exploiting their large component portfolio for enabling GHz-bandwidth and low-energy neurons. Progressing in tight synergy with appropriate training techniques, this evolution has already started to translate into performance improvements in end-to-end applications, highlighting the practical perspectives of the new neural network hardware when effectively synergized with new training frameworks. Herein, we present a complete portfolio of neuromorphic photonic subsystems and architectures, highlighting their utilization in practical application scenario for time series classification and fiber transmission links. Our work extends along feed-forward and recurrent photonic NN models, demonstrating experimental results together with the required training methods for bridging the gap between software-deployed NNs and the photonic hardware. We report on the experimentally validated performance of a 10GHz photonic time series classification engine, presenting also preliminary results on how photonic neurons can replace DSP modules in end-to-end fiber transmission schemes. The perspectives of these layouts to yield energy and area efficiency benefits are discussed through a detailed energy and area breakdown of neuromorphic photonic technologies, highlighting a promising roadmap when plasmo-photonic hardware is adopted.
Optical refractive index (RI) sensors exploiting selective co-integration of plasmonics with silicon photonics in Lab-on-achip configurations are expected to disrupt Point-of-Care (POC) diagnostics, delivering performance and economic breakthroughs. Propagating surface-plasmon-polariton modes offer superior sensitivity due to their extreme overlap with the surrounding medium. In parallel, low-loss photonics act as the hosting platform with which the plasmonic losses can be sustained while allowing for multiplexed layouts via in-plane SPP excitation schemes. However, merging plasmonics with silicon photonics in a cost-effective manner, requires a truly CMOS-compatible manufacturing process. Herein, we demonstrate experimentally, the highest bulk-sensitivity among all the plasmo-photonic interferometric RI sensors, while taking the leap forward in the development of a CMOS-manufactured plasmo-photonic sensing platform merging Si3N4 photonics and aluminum plasmonics. The proposed structure relies on a butt-coupled interface between Si3N4 waveguides and a 70 μm long plasmonic stripe, deployed in one branch of a Mach-Zehnder Interferometer (MZI) serving as the sensing transducer that detects local changes in the refractive index. The lower MZI arm (reference arm) exploits the low-loss Si3N4 platform to deploy a MZI-based variable optical attenuator followed by a thermo-optic phase shifter to optimize the sensor performance achieving resonance extinction ratio values at the MZI output of more than 35 dB. Experimental evaluation of a gold-based sensor revealed a bulk refractive index sensitivity of 1930 nm/RIU. In addition, we experimentally demonstrate that the proposed plasmo-photonic waveguide platform can migrate from gold (Au) to Aluminum (Al), demonstrating the first step towards a fully CMOS compatible plasmo-photonic interferometric sensor.
The identification of neuromorphic computing as a highly promising alternative computing system has been emerged from its potential to increase rapidly the computational efficiency that is currently restricted by Moore’s law end. First electronic neuromorphic chips like IBM’s TrueNorth and Intel’s Loihi revealed a tremendous performance improvement in terms of computational speed and density; however, they are still operating in MHz rates. To this end, neuromorphic photonic integrated circuits can further increase the computational speed and density, having a large portfolio of components with GHz-bandwidth and low-energy. Herein, we present an all-optical sigmoid activation function as well as a single-λ linear neuron. The all-optical sigmoid activation function comprises a Semiconductor Optical Amplifier-Mach-Zehnder Interferometer (SOA-MZI) configured in differentially-biased scheme followed by an SOA. Its thresholding capabilities have been experimentally demonstrated with 100psec optical pulses. Then, we introduce an all-optical phase-encoded weighting scheme and we experimentally demonstrate its linear algebra operational credentials by the means of a typical IQ modulator operated at 10Gbaud/s.
Plasmonic sensors, leveraging the profound exposure of propagating Surface-Plasmon-Polariton (SPP) modes over metal stripes to test analytes, became so far the “gold-standard” in plasmonic biosensing resulting in commercial available devices. However, a series of challenges associated with their bulky prism-based coupling configuration as well as their high optical losses need to be overcome in order to allow for miniaturized and multiplexed sensor layouts. In this context, selective co-integration of plasmonics with low-loss silicon-nitride photonics emerges as a promising solution towards addressing these challenges yet reaping the benefits from both technologies. In this work, we present an interferometric sensor based on a Mach-Zehnder device, where a “plasmo-photonic” waveguide branch is utilized to interrogate changes in the refractive index of a test analyte exploiting the accumulated phase change of the SPP mode being exposed in an aqueous solution. More specifically, the “plasmo-photonic” Mach-Zehnder sensor incorporates a gold plasmonic stripe with a length of 70 μm and a width of 7 μm that has been interfaced with Si3N4 waveguides by means of a butt-coupled interface. By conducting numerical simulations and considering the dispersion properties of the involved materials, we optimized the structural parameters of the sensor aiming at ultra-high bulk sensitivity in the order of micrometres per Refractive Index Unit (RIU).
Plasmonics have been identified as an ideal platform for ultra-sensitive, label-free biosensors mainly due to the high field confinement on a metal-dielectric interface and the resulting strong light-matter interaction offered by surface plasmon resonances (SPRs) that can be entirely exposed to test analytes. Well-established SPR-based biosensors exploiting propagating SPRs yield superior specifications regarding bulk sensitivity compared to localized counterparts leading to already commercial available sensor devices. However, most of these systems require bulky prism-based configurations to couple light into the Surface Plasmon Polariton (SPP) mode impeding system miniaturization. In addition, SPR-based sensors suffer from intrinsic high propagation losses restricting the potential for multiple on-chip functionalities. In this context, co-integration of plasmonics with a low-loss photonic platform emerges as a viable solution towards highly sensitive, low-loss and small footprint optical sensors. In this work, we present an ultra-compact, interferometric plasmonic sensor co-integrated on a TiO2 photonic waveguide platform. The device consists of two access TiO2 photonic waveguides separated by a gold-based metal stripe which is located on top of an appropriately shorter TiO2 waveguide layer. Two metal/insulator interfaces are formed at the top (sensing arm) and bottom surfaces (reference arm) of the metal able to support SPP modes which upon excitation through the input photonic waveguide propagate along the two metal surfaces and interfere at the output waveguide realizing a single-arm Mach-Zehnder Interferometer. After optimization of the device in aqueous environment, we achieved sensitivity values as high as 2430 nm/RIU at near-infrared spectrum region for a 65 um long plasmonic stripe.
Silicon photonics technology has emerged as a viable solution for the demonstration of highly functional Photonic Integrated Circuits (PICs) relying on the mixture of light sources with silicon based waveguides. However, the incorporation of the laser sources in all PICs has always been at the center of industrial and research attention. To date, the vast majority of such merging schemes focus on either flip chip bonding of external III-V dies or hybrid-integration techniques that feature very good optical performance at the expense of fabrication cost. The next evolution of PICs, however will rely on the monolithic integration of the III-V lasers on the silicon substrates for simultaneous optimization of cost and circuit performance. In this work two low-loss coupling interface schemes are presented for efficient light transition between monolithically integrated InP-based laser sources and a Si3N4 passive circuitry through an intermediate waveguiding layer. For both coupling interface schemes, the light is butt-coupled from the III-V source into an intermediate waveguide that in turn couples the light into the final Si3N4 waveguide platform utilizing an evanescent coupling scheme. Two approaches are investigated towards this direction: The first approach is based on a purely stoichiometric Si3N4 waveguide, while the second one is based on a Si-Rich Nitride (SRN) acting as the intermediate layer. In both cases 2D-FDTD simulations verified by 3D-FDTD simulation results reveal total transition losses of less than 1.7dB for the pure-Si3N4 and less than 1dB for the SRN approach.
Publisher’s Note: This conference presentation, originally published on 14 December 2017, was withdrawn per author request
Silicon photonics meet most fabrication requirements of standard CMOS process lines encompassing the photonics-electronics consolidation vision. Despite this remarkable progress, further miniaturization of PICs for common integration with electronics and for increasing PIC functional density is bounded by the inherent diffraction limit of light imposed by optical waveguides. Instead, Surface Plasmon Polariton (SPP) waveguides can guide light at sub-wavelength scales at the metal surface providing unique light-matter interaction properties, exploiting at the same time their metallic nature to naturally integrate with electronics in high-performance ASPICs.
In this article, we demonstrate the main goals of the recently introduced H2020 project PlasmoFab towards addressing the ever increasing needs for low energy, small size and high performance mass manufactured PICs by developing a revolutionary yet CMOS-compatible fabrication platform for seamless co-integration of plasmonics with photonic and supporting electronic. We demonstrate recent advances on the hosting SiN photonic hosting platform reporting on low-loss passive SiN waveguide and Grating Coupler circuits for both the TM and TE polarization states. We also present experimental results of plasmonic gold thin-film and hybrid slot waveguide configurations that can allow for high-sensitivity sensing, providing also the ongoing activities towards replacing gold with Cu, Al or TiN metal in order to yield the same functionality over a CMOS metallic structure. Finally, the first experimental results on the co-integrated SiN+plasmonic platform are demonstrated, concluding to an initial theoretical performance analysis of the CMOS plasmo-photonic biosensor that has the potential to allow for sensitivities beyond 150000nm/RIU.
Bringing photonics and electronics into a common integration platform can unleash unprecedented performance capabilities in data communication and sensing applications. Plasmonics were proposed as the key technology that can merge ultra-fast photonics and low-dimension electronics due to their metallic nature and their unique ability to guide light at sub-wavelength scales. However, inherent high losses of plasmonics in conjunction with the use of CMOS incompatible metals like gold and silver which are broadly utilized in plasmonic applications impede their broad utilization in Photonic Integrated Circuits (PICs). To overcome those limitations and fully exploit the profound benefits of plasmonics, they have to be developed along two technology directives. 1) Selectively co-integrate nanoscale plasmonics with low-loss photonics and 2) replace noble metals with alternative CMOS-compatible counterparts accelerating volume manufacturing of plasmo-photonic ICs. In this context, a hybrid plasmo-photonic structure utilizing the CMOS-compatible metals Aluminum (Al) and Copper (Cu) is proposed to efficiently transfer light between a low-loss Si3N4 photonic waveguide and a hybrid plasmonic slot waveguide. Specifically, a Si3N4 strip waveguide (photonic part) is located below a metallic slot (plasmonic part) forming a hybrid structure. This configuration, if properly designed, can support modes that exhibit quasi even or odd symmetry allowing power exchange between the two parts. According to 3D FDTD simulations, the proposed directional coupling scheme can achieve coupling efficiencies at 1550nm up to 60% and 74% in the case of Al and Cu respectively within a coupling length of just several microns.
Plasmonic technology has attracted intense research interest enhancing the functional portfolio of photonic integrated circuits (PICs) by providing Surface-Plasmon-Polariton (SPP) modes with ultra-high confinement at sub-wavelength scale dimensions and as such increased light matter interaction. However, in most cases plasmonic waveguides rely mainly on noble metals and exhibit high optical losses, impeding their employment in CMOS processes and their practical deployment in highly useful PICs. Hence, merging CMOS compatible plasmonic waveguides with low-loss photonics by judiciously interfacing these two waveguide platforms appears as the most promising route towards the rapid and costefficient manufacturing of high-performance plasmo-photonic integrated circuits. In this work, we present butt-coupled plasmo-photonic interfaces between CMOS compatible 7μm-wide Aluminum (Al) and Copper (Cu) metal stripes and 360×800nm Si3N4 waveguides. The interfaces have been designed by means of 3D FDTD and have been optimized for aqueous environment targeting their future employment in biosensing interferometric arrangements, with the photonic waveguides being cladded with 660nm of Low Temperature Oxide (LTO) and the plasmonic stripes being recessed in a cavity formed between the photonic waveguides. The geometrical parameters of the interface will be presented based on detailed simulation results, using experimentally verified plasmonic properties for the employed CMOS metals. Numerical simulations dictated a coupling efficiency of 53% and 68% at 1.55μm wavelength for Al and Cu, respectively, with the plasmonic propagation length Lspp equaling 66μm for Al and 75μm for Cu with water considered as the top cladding. The proposed interface configuration is currently being fabricated for experimental verification.
As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption.
Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on–chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.
Plasmonic technology has emerged as the most promising candidate to revolutionize future photonic-integrated-circuits (PICs) and deliver performance breakthroughs in diverse application areas by providing increased light-matter interaction at the nanometer scale, overcoming the diffraction limit. However, high insertion losses of plasmonic devices impede their practical deployment in PICs. To overcome this hurdle, selective integration of individual plasmonic devices on low-loss photonic platforms is considered, allowing for enhanced chip-scale functionalities with realistic power budgets. In this context, highly-efficient and fabrication-tolerant optical interfaces for co-planar plasmonic and photonic waveguides become essential, bridging these two “worlds” and ease combined high-volume manufacturing. Herein, a TM-mode butt-coupled interface for stoichiometric Si3N4 and Au-based thin-film plasmonic waveguides is proposed aiming to be utilized for bio-sensing applications. Following a systematic design process, this new configuration has been analyzed through 3D FDTD numerical simulations demonstrating coupling efficiencies up to 64% at the wavelength of 1.55 μm, with increased fabrication tolerance compared to silicon based waveguide alternatives.
Slot-based plasmonic waveguides have attracted significant attention owing to their unique ability to confine light within nanometer-scale. In this context, enhanced localized light-matter interaction and control have been exploited to demonstrate novel concepts in data communication and sensing applications revealing the immense potential of plasmonic slot waveguides. However, inherent light absorption in the metallic parts included is such structures hampers the scaling of plasmonic devices and limits their application diversity. A promising solution of such issues is the use of hybrid plasmo-photonic configurations. Hybrid slot waveguides have been introduced as the means to reduce such propagation losses while maintaining their functional advantages. In addition, their co-integration with low-loss photonic waveguides can enable the development of more complex structures with acceptable overall losses. In such scenario, light needs to be efficiently transferred from the photonic to the plasmonic components and/or backwards. Based on this rationale, in this work a hybrid slot-based structure is adopted to achieve highly efficient light transfer between photonic and plasmonic slot waveguides in the near-infrared spectrum region (λ=1550 nm). This transition is realized with the aid of a directional coupling scheme. For this purpose, a Si3N4 bus waveguide (photonic branch) is located below an Aubased metallic slot (plasmonic branch) forming a hybrid waveguide element. The combined configuration, as it is shown with the aid of numerical simulations , is capable of supporting two hybrid guided modes with quasi-even and odd symmetry allowing the development of a power exchange mechanism between the two branches. In this context, a new directional coupling structure has been designed which can achieve power transmission per transition over 68% within a coupling length of the order of just several microns.
Hybrid integration of VCSELs onto silicon-on-insulator (SOI) substrates has emerged as an attractive approach for bridging the gap between cost-effective and energy-efficient directly modulated laser sources and silicon-based PICs by leveraging flip-chip (FC) bonding techniques and silicon grating couplers (GCs). In this context, silicon GCs, should comply with the process requirements imposed by the complimentary-metal-oxide-semiconductor manufacturing tools addressing in parallel the challenges originating from the perfectly vertical incidence. Firstly, fully etched GCs compatible with deep-ultraviolet lithography tools offering high coupling efficiencies are imperatively needed to maintain low fabrication cost. Secondly, GC's tolerance to VCSEL bonding misalignment errors is a prerequisite for practical deployment. Finally, a major challenge originating from the perfectly vertical coupling scheme is the minimization of the direct back-reflection to the VCSEL’s outgoing facet which may destabilize its operation. Motivated from the above challenges, we used numerical simulation tools to design an ultra-low loss, bidirectional VCSEL-to-SOI optical coupling scheme for either TE or TM polarization, based on low-cost fully etched GCs with a Si-layer of 340 nm without employing bottom reflectors or optimizing the buried-oxide layer. Comprehensive 2D Finite-Difference-Time- Domain simulations have been performed. The reported GC layout remains fully compatible with the back-end-of-line (BEOL) stack associated with the 3D integration technology exploiting all the inter-metal-dielectric (IMD) layers of the CMOS fab. Simulation results predicted for the first time in fully etched structures a coupling efficiency of as low as -0.87 dB at 1548 nm and -1.47 dB at 1560 nm with a minimum direct back-reflection of -27.4 dB and -14.2 dB for TE and TM polarization, respectively.
In view of high volume manufacturing of silicon based photonic-integrated-circuits (Si-PICs), CMOS compatible low-cost fabrication processes as well as simplified packaging methods are imperatively needed. Silicon-onInsulator (SOI) based grating couplers (GCs) have attracted attention as the key components for providing optical interfaces to Si-PICs due their fabrication simplicity compared to the edge coupling alternatives. GCs based on perfectly vertical coupling scheme become essential by introducing substantial savings in the packaging cost as no angular configurations are required but at the expense of high coupling efficiency values due to the second order diffraction. In this context, research efforts concentrated on designing GCs with minimized back reflection into the waveguide yet employing more than one etching steps or rather complex fabrication processes. Herein, we propose a fully etched CMOS compatible non-uniform one-dimensional (1D) GC for perfectly vertical coupling with low back reflected optical power by means of numerical simulations. A particle-swarm-optimization (PSO) algorithm was deployed in conjunction with a commercially available 2D finite-difference-time-domain (FDTD) method to maximize the coupling efficiency to a SMF fiber for TM polarization. The design parameters were restricted to the period length and the filling factor while the minimum feature size was 80 nm. A peak coupling loss of 4.4 dB at 1553 nm was achieved with a 1-dB bandwidth of 47 nm and a back reflection of -20 dB. The coupling tolerance to fabrication errors was also investigated.
Silicon-photonic 2×2 electro-optical switching elements and modulators based on the carrier depletion mechanism using both dual-resonator and MZI layout configurations have been developed. The passive photonic structures were developed and optimized using a fast design-fabrication-characterization cycle. The main objective is to deliver smallfootprint, low-loss and low-energy silicon photonic electro-optical switching elements and modulators equipped with standard input-output grating couplers and radio-frequency electrical contact tips to allow their characterization in highspeed probe-station setups. The insertion losses, crosstalk, power consumption and BER performance will be addressed for each electro-optical structure. The fabrication steps, including low loss waveguide patterning, pn junction and low resistive ohmic contact formation have been optimized to produce high performance devices with relaxed fabrication tolerances, employing both optical and electron-beam lithography.
In this paper we present a uniform fully-etched TM-mode grating coupler for vertical coupling of light into SOI photonic integrated circuits and a chirped alternative to increase its bandwidth by using the same fabrication steps and maintaining its coupling efficiency. The first design refers to a uniform grating consisting of 22 periods with 670 nm period length, exhibiting 5.6 dB coupling losses at 1564 nm and a 3dB bandwidth of 32 nm. The 3dB bandwidth is extended from 32 to 76 nm by adding a chirped section at the front end of the uniform section in the second design. The ultra-wideband coupler can be used across all C-band as well as in S and L bands, it is realized at no expense of fabrication complexity while coupling efficiency is maintained. The coupling efficiency can be improved if the grating gap is decreased below 80 nm yet increasing fabrication resolution requirements. Theoretical and experimental analysis is presented for the coupling efficiency versus structure period and gap width while angle alignment tolerance is also investigated.
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