A low temperature amorphous silicon (a-Si) thin film transistor (TFT) and amorphous silicon PIN photodiode technology for flexible passive pixel detector arrays has been developed using active matrix display technology. The flexible detector arrays can be conformed to non-planar surfaces with the potential to detect x-rays or other radiation with an appropriate conversion layer. The thin, lightweight, and robust backplanes may enable the use of highly portable x-ray detectors for use in the battlefield or in remote locations. We have fabricated detector arrays up to 200 millimeters along the diagonal on a Gen II (370 mm x 470 mm rectangular substrate) using plasma enhanced chemical vapor deposition (PECVD) a-Si as the active layer and PECVD silicon nitride (SiN) as the gate dielectric and passivation. The a-Si based TFTs exhibited an effective saturation mobility of 0.7 cm2/V-s, which is adequate for most sensing applications. The PIN diode material was fabricated using a low stress amorphous silicon (a-Si) PECVD process. The PIN diode dark current was 1.7 pA/mm2, the diode ideality factor was 1.36, and the diode fill factor was 0.73. We report on the critical steps in the evolution of the backplane process from qualification of the low temperature (180°C) TFT and PIN diode process on the 150 mm pilot line, the transfer of the process to flexible plastic substrates, and finally a discussion and demonstration of the scale-up to the Gen II (370 x 470 mm) panel scale pilot line.
The U.S. Army, Arizona State University (ASU) and commercial industry have joined forces to create the Flexible Display Center (FDC) at Arizona State University, a large-scale collaborative venture designed to rapidly advance flexible display technology to the brink of commercialization. The Center has completed its startup phase and is now engaged in an intensive and aggressive applied research and development program that will produce high quality, high performance active matrix reflective and emissive flexible display technology demonstrators (TDs). Electrophoretic ink and cholesteric liquid crystals have been selected as Center reflective imaging layer technologies; these technologies are attractive because they are fully reflective and bistable (extremely low power) and because the materials are environmentally robust and intrinsically rugged. Organic light emitting devices (OLEDs) have been chosen as the emissive imaging layer technology. These three electro-optic subsystems will be integrated with a flexible a-Si thin film transistor active matrix backplane platform. We have created the integrated design, backplane fabrication, display assembly, test and evaluation capability to enable rapid cycles of learning and technology development. Backplane fabrication is currently accomplished on a 6” wafer scale pilot line linked to a Manufacturing Execution System and supported by a comprehensive suite of in-fab metrology tools. We are currently installing a GEN II pilot line, with qualified operation slated for 2006. This line will be used to demonstrate process and display form factor capability, while providing high yield low volume manufacturing of pilot-scale levels of technology demonstrators for the Army and our commercial partners.
There is an ever increasing need for lightweight, flexible, inexpensive integrated systems encompassing displays, sensors, computers, and other electronics to provide unprecedented information capability to a broad range of war-fighters. During the next few years, a team of experts will be engaged in an intensive development program pursuing a two-pronged goal: (1) to integrate and fabricate reflective and emissive systems such as organic light emitting devices on flexible substrates including plastics, and (2) to develop materials and structural platforms that allow flexible backplane electronics to be integrated with ancillaries and display components, as well as to be mass-produced economically. An underlying theme of this effort continues to be leveraging emerging processing techniques, for example a-Si and poly-Si thin film transistor (TFT) technologies, but also advanced micro-contact pattern transfer techniques for producing low cost product with molecular structures for combined communication and electronic appliances. The initial technology integration target is a 4” diagonal active matrix QVGA display on conformal plastic substrates. These advanced developments will be realized through a unique collaborative effort between the U.S. Army, Arizona State University (ASU) in close collaboration with its academic partners, and industry partners, who are united in our shared commitment to optimize the necessary production technologies for large area/large scale, low cost, cutting-edge display products and state-of-the-art manufacturing capabilities. The newly formed Flexible Display Center (FDC) at Arizona State University provides a one-of-a-kind environment fully dedicated to fulfill the major technical challenges not addressed by display manufacturers producing glass-based flat panel displays.
Metallization, and conductor systems in general, are a critical part of any VLSI chip, and as such can act to set limits on future down-scaling of such integrated circuits. Due to decreasing lateral and vertical dimensions, interconnections are rapidly becoming a problem in terms of device yield, reliability, signal delay time, and inter-device interactions. In this paper, we discuss how interconnection limitations will affect the scaling of advanced circuits. We will also cover a number of issues regarding the interconnection technologies that will be required in future ULSI circuits. The problems with conductor systems begin with the interconnection topology which provides constraints and limitations. The physical problems then begin with the deposition of the materials. For example, chemical vapor deposition of metal or metal-silicide interconnects causes several unique concerns due to surface chemistry, leading to undersirable reactions and compositional and structural nonuniformities. Similarly, factors such as control of step coverage are important for reduced geometries. Recent experiments and modeling techniques which address these problems will therefore be described. Lithographical aspects also pose problems in the scaling of metal lines and new pattern definition techniques will be discussed. Finally, isolation of information within dense crossing interconnects can become very difficult, with coupling causing degradation of information within localized devices.
Conference Committee Involvement (2)
Future Display Technologies II
20 April 2006 | Orlando (Kissimmee), Florida, United States
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