In this article the recent progress in the elements of EUV lithography is presented. Source power around 205W was demonstrated and further scaling up is going on, which is expected to be implemented in the field within 2017. Source availability keeps improving especially due to the introduction of new droplet generator but collector lifetime needs to be verified at each power level. Mask blank defect satisfied the HVM goal. Resist meets the requirements of development purposes and dose needs to be reduced further to satisfy the productivity demand. Pellicle, where both the high transmittance and long lifetime are demanded, needs improvements especially in pellicle membrane. Potential issues in high-NA EUV are discussed including resist, small DOF, stitching, mask infrastructure, whose solutions need to be prepared timely in addition to high-NA exposure tool to enable this technology.
As the design rule of Integrated Circuits(IC) becomes smaller, the precise measurement of Critical Dimension (CD) of
features and minimization of deviation in CD measured becomes a vital issue. In this paper, a simple frequency analysis
method to extract the noise from SEM images was used to evaluate the contribution of SEM noise in CD Uniformity.
Multiple SEM images of simple Line and Space (L/S) patterns were analyzed and a model of frequency profile (Power
Spectrum Density (PSD) model) was made using an offline analyzing tool based on Matlab®. From this profile, white
noise and 1/f profile were separated. Noises are eliminated to generate a noise reduced PSD profile to make CD results.
The contribution of white noise on CD measurement can be assessed using Line Width Roughness (LWR) measurement.
Furthermore, CD uniformity can be also predicted from the model. This prediction is based on an assumption that CD
uniformity is equal to LWR if the inspection area is extended to infinity and appropriate sampling method is applied. The
results showed that the contribution of white noise on LWR can be up to around 70% (in power) without any noise
reduction measures (sum line averaging) after imaging in photo resist image. For experimental validation, CD uniformity
is predicted from the model for different measurement conditions and compared with real measurement. For a result, CD
uniformity prediction (3sigma) from the model shows within 20% in accuracy with real CD uniformity value measured
from the photo resist image.
Overlay (O/L) misalignment (M/A) is induced from numerous sources including metrology error and stage control error,
and aberration in projection optics. However, as design rule become smaller, aberration induced O/L M/A is evaluated to
take considerable portion in the overlay budget. This paper focuses on O/L M/A issues from projection optics. We
presents a simulation analysis of M/A between contact hole (C/H) pattern and line & space (L/S) pattern at 65nm node
based on the aberration data from actual lithography tool to single out the main source of O/L M/A.. The study shows
that the aberration in projection optics can induce considerable M/A and the conventional overlay keys do not represent
this M/A properly. Among the Zernike fringe polynomials, the third-order behavior (D3) in Z2 (tilt) is found to be the
critical source of misalignment. This portion of the aberration is resulted from the lens heating (LH) and can be corrected.
However, this correction method needs improvements because its controllability over LH is not enough for the complete
correction of LH induced M/A. Besides D3, Z10 (3-Foil) are found to be the major sources for pattern shift in C/H
patterns, and Z7 and Z14 (Coma x) are found for L/S patterns.
Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and
Flash Imprint Lithography (S-FIL ®) is a unique method that has been designed from the beginning to enable precise
overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the
pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field
and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of
multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it
is critical to address the infrastructure associated with the fabrication of templates.
For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x
templates with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using commercial
variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing
these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing
technology for the sub 32nm node. Here we report the first imprinting results from sub-40 nm full-field patterns, using
Samsung's current flash memory production device design. The fabrication of the template is discussed and the
resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting
results are described in terms of CD uniformity, etch results, and overlay.
Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and
Flash Imprint Lithography (S-FIL (R)) is a unique patterning method that has been designed from the beginning to enable
precise overlay to enable multilevel device fabrication. A photocurable low viscosity resist is dispensed dropwise to
match the pattern density requirements of the device, thus enabling patterning with a uniform residual layer thickness
across a field and across multiple wafers. Further, S-FIL provides sub-50 nm feature resolution without the significant
expense of multi-element projection optics or advanced illumination sources. However, since the technology is 1X, it is
critical to address the infrastructure associated with the fabrication of imprint masks (templates).
For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x
imprint masks with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using
commercial variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route
to realizing these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive
manufacturing technology for the sub-32nm node. Here we report the first imprinting results from sub-40 nm full-field
patterns, using Samsung's current flash memory production device design. The fabrication of the imprint mask and the
resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting
results are described in terms of CD uniformity, etch results, and overlay.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.