Mr. Huan Ting Tseng Profile

Huan Ting Tseng

at United Microelectronics Corp

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Author

Publications (3)

Proceedings Article | 6 April 2007 Paper

Depth-of-focus (DOF) and line-width roughness (LWR) performance of novel surface conditioner solutions for immersion lithography

Bo Jou Lu, Yongfa Huang, H. Tseng, Chun Chi Yu, Ling-Jen Meng, Ming-Chi Liao, Michale Legenza

Proceedings Volume 6519, 651942 (2007) https://doi.org/10.1117/12.711938

KEYWORDS: Line width roughness, Etching, Photoresist processing, Optical proximity correction, Image processing, Semiconducting wafers, Immersion lithography, Lithography, Line edge roughness, Scanning electron microscopy

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Proceedings Article | 14 March 2006 Paper

Full-chip lithography manufacturability check for yield improvement

Yongfa Huang, Edward Tseng, Benjamin Szu-Min Lin, Chun Chi Yu, Chien-Ming Wang, Hua-Yu Liu

Proceedings Volume 6156, 61560W (2006) https://doi.org/10.1117/12.656401

KEYWORDS: Process modeling, Finite element methods, Semiconducting wafers, Data modeling, Photomasks, Lithography, Manufacturing, Calibration, Photoresist processing, Inspection

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Proceedings Article | 10 May 2005 Paper

The performances of different overlay mark types at 65nm node on 300-mm wafers

H. Tseng, Ling-Chieh Lin, I. Huang, Benjamin Lin, Chin-Chou Huang, Chien-Jen Huang

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.598424

KEYWORDS: Overlay metrology, Chemical mechanical planarization, Metrology, Semiconducting wafers, Tungsten, Optical alignment, Manufacturing, Metals, Image processing, Optical design

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The integrated circuit (IC) manufacturing factories have measured overlay with conventional "box-in-box" (BiB) or "frame-in-frame" (FiF) structures for many years. Since UMC played as a roll of world class IC foundry service provider, tighter and tighter alignment accuracy specs need to be achieved from generation to generation to meet any kind of customers' requirement, especially according to International Technology Roadmap for Semiconductors (ITRS) 2003 METROLOGY section1. The process noises resulting from dishing, overlay mark damaging by chemical mechanism polishing (CMP), and the variation of film thickness during deposition are factors which can be very problematic in mark alignment. For example, the conventional "box-in-box" overlay marks could be damaged easily by CMP, because the less local pattern density and wide feature width of the box induce either dishing or asymmetric damages for the measurement targets, which will make the overlay measurement varied and difficult. After Advanced Imaging Metrology (AIM) overlay targets was introduced by KLA-Tencor, studies in the past shown AIM was more robust in overlay metrology than conventional FiF or BiB targets. In this study, the applications of AIM overlay marks under different process conditions will be discussed and compared with the conventional overlay targets. To evaluate the overlay mark performance against process variation on 65nm technology node in 300-mm wafer, three critical layers were chosen in this study. These three layers were Poly, Contact, and Cu-Metal. The overlay targets used for performance comparison were BiB and Non-Segmented AIM (NS AIM) marks. We compared the overlay mark performance on two main areas. The first one was total measurement uncertainty (TMU)3 related items that include Tool Induced Shift (TIS) variability, precision, and matching. The other area is the target robustness against process variations. Based on the present study AIM mark demonstrated an equal or better performance in the TMU related items under our process conditions. However, when non-optimized tungsten CMP was introduced in the tungsten contact process, due to the dense grating line structure design, we found that AIM mark was much more robust than BiB overlay target.

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