Mr. Hyoung-Soon Yune Profile

Hyoung-Soon Yune

Member, Research Staff at SK Hynix Inc

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Author

Publications (14)

Proceedings Article | 20 March 2018 Presentation + Paper

Model-assisted template extraction SRAF application to contact holes patterns in high-end flash memory device fabrication

Ahmed Seoud, Juhwan Kim, Yuansheng Ma, Srividya Jayaram, Le Hong, Gyu-Yeol Chae, Jeong-Woo Lee, Dae-Jin Park, Hyoung-Soon Yune, Se-Young Oh, Chan-Ha Park

Proceedings Volume 10587, 105870L (2018) https://doi.org/10.1117/12.2297659

KEYWORDS: SRAF, Lithography, Optical proximity correction, Optical lithography

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Proceedings Article | 16 March 2016 Paper

Process window variation comparison between NTD and PTD for various contact type

Doyoun Kim, Hyoungsoon Yune, Daejin Park, Joohong Jeong, Woosung Moon, Mingu Kim, Seyoung Oh, Chanha Park, Hyunjo Yang

Proceedings Volume 9780, 97800D (2016) https://doi.org/10.1117/12.2218858

KEYWORDS: Lithography, Source mask optimization, Optical lithography, Semiconducting wafers, Wafer-level optics, Critical dimension metrology, Ultraviolet radiation, Image compression, Photomasks, Atrial fibrillation

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Proceedings Article | 12 April 2013 Paper

Mask 3D effects on contact layouts of 1Xnm NAND flash devices

Jongwon Jang, Hyungjeong Jeong, Hyungsoon Yune, Seyoung Oh, Hyunjo Yang, Donggyu Yim

Proceedings Volume 8683, 86831V (2013) https://doi.org/10.1117/12.2011659

KEYWORDS: SRAF, Photomasks, Optical proximity correction, Metals, Modulation, Scanning electron microscopy, Scanners, Cadmium sulfide, Semiconducting wafers, Double patterning technology

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Proceedings Article | 23 March 2011 Paper

Study of model-assisted rule base SRAF for random contact

James Moon, Byoung-Sub Nam, Cheol-Kyun Kim, Hyong-Sun Yun, Ji-Young Lee, Donggyu Yim, Sung-Ki Park

Proceedings Volume 7973, 79732H (2011) https://doi.org/10.1117/12.879201

KEYWORDS: SRAF, Optical proximity correction, Semiconducting wafers, Photomasks, Performance modeling, Electroluminescence, Mask making, Scanning electron microscopy, Wafer testing, Lithography

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Proceedings Article | 23 March 2011 Paper

Study of various RET for process margin improvement in 3Xnm DRAM contact

Hak-Yong Sim, Hyoung-Soon Yune, Yeong-Bae Ahn, James Moon, Byoung-Sub Nam, Donggyu Yim, Sung-Ki Park

Proceedings Volume 7973, 79732N (2011) https://doi.org/10.1117/12.879206

KEYWORDS: Photomasks, Resolution enhancement technologies, Electroluminescence, Optical lithography, Semiconducting wafers, Mask making, Scanning electron microscopy, Lithography, Double patterning technology, Image processing

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Proceedings Article | 4 December 2008 Paper

CD uniformity improvement of sub 60nm contact hole using model based OPC

Hyoung-Soon Yune, Yeong-Bae Ahn, Jung-Chan kim, Hye-Jin Shin, Gyun Yoo, James Moon, Byoung-Sub Nam, Donggyu Yim

Proceedings Volume 7140, 71403E (2008) https://doi.org/10.1117/12.804654

KEYWORDS: Optical proximity correction, Critical dimension metrology, Model-based design, Data modeling, Calibration, Semiconducting wafers, Photomasks, Resolution enhancement technologies, Etching, Instrument modeling

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Proceedings Article | 4 December 2008 Paper

Novel process proximity correction by the pattern-to-pattern matching method with DBM

Dae-Jin Park, Jinyoung Choi, Hyoungsoon Yune, Jaeseung Choi, Cheolkyun Kim, Bong-Ryoul Choi, Donggyu Yim

Proceedings Volume 7140, 71403K (2008) https://doi.org/10.1117/12.804660

KEYWORDS: Critical dimension metrology, Optical proximity correction, Transistors, Semiconducting wafers, Etching, Error analysis, Data modeling, Thermal effects, Databases, Metrology

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Proceedings Article | 26 March 2007 Paper

Application of full-chip optical proximity correction for sub-60-nm memory device in polarized illumination

Hyoung-Soon Yune, Yeong-Bae Ahn, Dong-jin Lee, James Moon, Byung-Ho Nam, Dong-gyu Yim

Proceedings Volume 6520, 65201R (2007) https://doi.org/10.1117/12.711977

KEYWORDS: Optical proximity correction, Polarization, Calibration, Critical dimension metrology, Data modeling, Lithographic illumination, Resolution enhancement technologies, Lithography, Semiconducting wafers, Line edge roughness

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Proceedings Article | 14 March 2006 Paper

Highly accurate hybrid-OPC method for sub-60nm memory device

Hyoung-Soon Yune, Cheol-Kyun Kim, Yeong-Bae Ahn, Byung-Ho Nam, Donggyu Yim

Proceedings Volume 6156, 61561A (2006) https://doi.org/10.1117/12.656853

KEYWORDS: Optical proximity correction, Data modeling, Model-based design, Calibration, Photomasks, Tolerancing, Process modeling, Instrument modeling, Resolution enhancement technologies, Semiconducting wafers

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Proceedings Article | 8 November 2005 Paper

Hybrid ORC method for low K1 process

Byungho Nam, Jaeseung Choi, Yeongbae Ahn, Cheolkyun Kim, Hyoungsoon Yune, James Moon, Donggyu Yim, Jinwoong Kim

Proceedings Volume 5992, 59922T (2005) https://doi.org/10.1117/12.632023

KEYWORDS: Optical proximity correction, Critical dimension metrology, Data modeling, Bridges, Inspection, Semiconducting wafers, Calibration, Etching, Mathematical modeling, Photomasks

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Proceedings Article | 30 July 2002 Paper

Double-exposure strategy using OPC and simulation and the performance on wafer with sub-0.10-um design rule in ArF lithography

Se-Young Oh, Wan-Ho Kim, Hyoung-Soon Yune, Hee-Bom Kim, Seo-Min Kim, Chang-Nam Ahn, Ki-Soo Shin

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474541

KEYWORDS: Optical proximity correction, Lithography, Semiconducting wafers, Double patterning technology, Optical lithography, Reticles, Device simulation, Electroluminescence, Image processing, Lithographic illumination

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As the pattern size becomes smaller, double or multi exposure is required unless the epochal solutions for overcoming the limits of present lithography system do appear or are discovered. ArF DET (double exposure technology) strategy based on manual OPC with in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method to extend the limitation of current lithography. HOST requires no additional procedures and separate layout optimizations of each region in terms of OPC are enough. Furthermore, it is possible to change illumination condition of each region and the overlap between two regions with ease. The results from the simulation are pattern size and profile of each condition according to the defous and misregistration. 0.63 NA ArF Scanner and Clariant resist is used for wafer process. The resist was coated on Clariant organic BARC using 0.24 um thickness. Dipole illumination for cell region and annular illumination for peripheral region are used. Cell region contains 0.20 um pitch duty pattern and peripheral region 0.24 um pitch duty pattern. The boundary of two regions is investigated in view of validity of stitching itself. The layout of reticles used as the cell and peripheral region are optimized by OPC, respectively and then, additional OPC was treated to the boundary, i.e., stitching area to compensate the cross term of the boundary caused by separate and independent optimization with OPC in the cell and the peripheral regime. The final patterns were acquired by defining the cell at first and the peripheral region secondly with different defocus and registration in respect to the cell. The actual data on wafer are presented according to defocus and one region's overlay offset relatively to the other region. And the outstanding matching between simulation results and in-line data are shown. Lithography process window for stable patterning is thoroughly investigated in view of depth of focus, energy latitude, registration between two stitched regions and stitching itself in the boundary. It is found from the experiment that total DOF of DE (double exposure) is 0.5 um and the total EL of DE is 10.0% in this paper. At present, it is very difficult to ensure stable process margin for the sub-0.10 um patterning. But there is a promising technology called stitching with special optimization. In addition, this technology will be nominated as an eternal candidate process whenever our lithography is in the adversity at the limits of his days.

Proceedings Article | 14 September 2001 Paper

Application of full-chip level optical proximity correction to memory device with sub-0.10-um design rule and ArF lithography

Hyoung-Soon Yune, Hee-Bom Kim, Wan-Ho Kim, Chang-Nam Ahn, Young-Mog Ham, Ki-Soo Shin

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435724

KEYWORDS: Optical proximity correction, Photomasks, Lithography, Semiconducting wafers, Critical dimension metrology, Model-based design, Data modeling, Reticles, Process modeling, Image processing

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Recently, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as cell region to the resolution limit of exposure tools. Therefore it is necessary to apply optical proximity correction (OPC) not only to the patterns in cell region but also to those in peripheral region. It is impossible to apply manual OPC method in peripheral region. Because the peripheral region is composed of random patterns with large data volume, and it takes too long execution time with manual OPC. For random pattern OPC in peripheral region, automatic OPC tool is required. Now for the automatic OPC tool, model-based and rule-based methods are developed for the commercial use. In this paper, the effectively applicable process is discussed using model-based method in automatic OPC at the sub-0.10 micrometer design rule in ArF lithography. For the application of automatic OPC tool at the design rule of sub-0.10 micrometer and ArF process in memory devices the following problem should be cleared. In small size of design rule, we should consider not only pattern fidelity but also process margin such as depth of focus (DOF) and exposure latitude (EL) at the cell OPC. But automatic OPC tool is insufficient to be applied for cell region OPC, because it considers not process margin but pattern fidelity and it has low accuracy using much approximation model to reduce layout correction time. To solve this problem, we suggest a full chip OPC process using both automatic OPC tool and the manual OPC method using the novel lithography simulation model (Diffused Aerial Image Model, DAIM). DAIM is available to predict wafer pattern and process margin of cell, its accuracy is verified in ArF process as in KrF process. We could see small standard deviation error between experiment and DAIM in ArF process using various line or space patterns, which is about 9 nm at binary intensity mask (BIM). So the manual OPC with DAIM resulted in the wide process margin and good pattern fidelity overcoming the limitation of automatic OPC tool. However it is necessary to correlate energy level of DAIM for cell region OPC with that of the model in the automatic OPC tool for peripheral region OPC, because cell and peripheral region are exposed with the same exposure dose in stepper or scanner. In case of ArF process, we could see the small difference of energy level and standard deviation error, which is about 1.4%, 2 nm at BIM and 6.3%, 3 nm at half-tone phase shift mask (PSM), between DAIM and automatic OPC tool. As the result of using DAIM and automatic OPC tool simultaneously at full chip OPC, we could see improved results from cell to peripheral region at the sub-0.10 micrometer design rule in ArF lithography.

Proceedings Article | 22 January 2001 Paper

Potentialities of sub-100-nm optical lithography of alternating and phase-edge phase-shift mask for ArF lithography

Sang-Sool Koo, Hee-Bom Kim, Hyoung-Soon Yune, Jee-Suk Hong, Seung-Weon Paek, Tae-Seung Eom, Chang-Nam Ahn, Young-Mog Ham, Ki-Ho Baik, Kyu-Yong Lee, Lee-Ju Kim, Hong-Seok Kim

Proceedings Volume 4186, (2001) https://doi.org/10.1117/12.410711

KEYWORDS: Lithography, Photomasks, Critical dimension metrology, Phase shifts, Electroluminescence, Optical lithography, Chromium, Etching, Mask making, Scanning electron microscopy

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Proceedings Article | 5 July 2000 Paper

Accuracy of diffused aerial image model for full-chip-level optical proximity correction

Jee-Suk Hong, Hee-Bom Kim, Hyoung-Soon Yune, Chang-Nam Ahn, Young-Mo Koo, Ki-Ho Baik

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.388936

KEYWORDS: Optical proximity correction, Photoresist processing, Lithography, Diffusion, Critical dimension metrology, Image processing, Photomasks, Cadmium, Error analysis, Deep ultraviolet

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Showing 5 of 14 publications

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