KEYWORDS: Lithography, Silicon, Manufacturing, Photomasks, Product engineering, Semiconducting wafers, Semiconductors, Transistors, Field programmable gate arrays, System on a chip
Following Moore's Law semiconductor industry is going through a challenging transition from 180 nm to 130 nm manufacturing process geometries and rapidly approaching 90 nm geometries. The major challenges associated with the transition to nanometer design include:
(1) Increasing design sizes and complexity (e.g. 300-400M transistors for FPGAs);
(2) Increasing number of design rules (approaching 2000 for advanced 90 nm processes);
(3) Increasing design cycle (4-9 months for ASICs);
(4) Increasing design cost (advanced design flow cost $15M+).
With the size and complexity of today's advanced ASICs and SoCs, the ability of designers to efficiently fix DRC errors is becoming a critical challenge impacting productivity and time-to-market. Designers need new EDA tools to process designs of very high complexity in shorter time. New tools should bridge design and process worlds by transparently providing designers with more detailed process (lithography) information. In this paper the authors will describe a method for manufacturing verification of automated design rule fixes. Many types of design rule violation are detected, automatically fixed, and verified by lithography simulation.
The X Architecture is a novel on-chip interconnect architecture based on the pervasive use of diagonal wiring. This diagonal wiring reduces total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power, a cost. Thirty percent or greater reduction in via counts is a compelling feature for IC design - but can chips with massive amounts of diagonal wiring be manufactured without some other penalty? This paper presents the result of a project, collaborated by Cadence Design Systems, Numerical Technologies, DuPont Photomasks, and Nikon, aimed at optimizing each step of the lithography supply chain for the Architecture from masks to wafers at 130 nm.
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