Superconducting optoelectronic networks are a promising route to large-scale neuromorphic computing. Using light for communication at the single-photon level overcomes fan-out challenges of electrical communication while achieving the minimum possible latency and lowest possible light levels. Such communication can be achieved with synapses based on superconducting single-photon detectors. Performing computations with superconducting Josephson junctions offers simple instantiations of synaptic, dendritic, and neuronal functions, and Josephson junctions have the highest speed over energy quotient of any known active circuit element. There is no known method to compute faster with less energy. This talk will summarize experimental demonstrations of single-photon communication links in silicon photonics, multiplanar waveguide routing networks, single-photon synapses and their associated memory circuits, optoelectronic dendrites, and superconductor-semiconductor interfaces that drive the light sources. Training algorithms that make such networks useful for artificial intelligence applications will be presented.
We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a “More-than- Moore” technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.
We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in
unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process –
the same process used to make many commercially available microprocessors including the IBM Power7 and Sony
Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available,
which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices
with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the
constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to
create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby
eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline
silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the
full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting
electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of
a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically
integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic
transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of
photonics into the microprocessor.
1.278μm laser emission has been observed in a SOI structure which has been nanopatterned to contain an array
of nanopores. The optical transition is identified to be associated with phononless recombination mediated by
the bistable, carbon-related G center. The present work is focused on increasing the luminescence intensity
from nanopatterned Si by increasing the number of G centers present in the material. The G center density is
increased by increasing the concentration of substitutional atoms in the lattice prior to nanopatterning. To this
end, solid-phase epitaxial regrowth of carbon-rich silicon is utilized in order to take advantage of the increased
solid solubility of carbon in silicon at the interface between crystalline and amorphous solid silicon.
1.278μm laser emission has been observed in a SOI structure which has been nanopatterned to contain an array
of nanopores. The optical transition is known to be associated with phononless recombination mediated by
the bistable, carbon-related G-center. A physical model is proposed to explain the enhanced optical activity
of the G-centers in the presence of the nanopore array. The effects of the SOI, strain, dielectric modification
and breaking of phonon k-selection rules on the optical properties of the nanopatterned silicon are addressed.
Temperature limitations are discussed.
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