This paper presents an effective methodology for etch PPC (Process Proximity Correction) of 20 nm node
DRAM (Dynamic Random Access Memory) gate transistor. As devices shrinks, OCV(On chip CD Variation)
control become more important to meet the performance goal for high speed in DRAM. The main factors which
influence OCV are mask, photo, etch PPE (Process proximity effect) in DRAM gate. Model based etch PPC is
required to properly correct Etch PPE as device density increases. To improve OCV in DRAM gate, we applied
new type of etch loading kernel. It is called Vkernel which accounts for directional weight from the point of
interest. And we optimized the etch PPC convergence by optimizing the etch PPC iteration. Because of density
difference between spider mask and real gate mask, the skew difference occurs between them. We tested the
effect of long range density using same real gate pattern clip by varying mask open image size from 0.5 ~ 10
mm. The ADI CD difference was on average in the order on 2 nm for varying mask open image size. But the
ACI CD difference (the average of CD range by varying open image size) was very noticeable (about 15 nm).
This result shows that etch skew affected by long range density by mm unit size. Due to asymmetrical pattern in
real gate mask, spider mask which have symmetrical patterns is necessarily used to make PPC model. The etch
skew of real pattern clip in spider mask was not also the same for the real pattern in real gate mask. To reduce
this skew difference between spider mask and real mask, we applied open field mask correction term and long
range density effects correlation equation to PPC modeling. There was noticeable improvement in the accuracy
of PPC model. By applying these improvement items, OCV of 20 nm node DRAM gate is shown to improve up
to 67%.
As the design technology node becomes smaller, k1 factor is decreasing below 0.3 and optical proximity correction
(OPC) divergence is increasing. The gate critical dimension (CD) control and systematic defect inspection is becoming
critical to improving circuit yield. For more accurate OPC verification and systematic defect inspection, design based
metrology become increasingly important, because accuracy of simulation based OPC model verification has its
limitation. In this paper, we used NGR-2100 as a design based metrology tool to confirm the accuracy of OPC modeling
and process window qualification. NGR-2100 uses high energy wide-beam for high speed secondary electron sampling
and large field of view. It can measure full chip CD distribution and more accurate process window compared to optical
inspection tool. Because of using high energy beam, conducting layer like carbon film should be coated on photo resist
patterned sample wafer to prevent local electron charging. However, coated carbon may increase CD variation. By using
atomic layer deposition-type TiN layer instead of carbon, CD variation could be reduced.
Boundary Layer Model (BLM) is applied to OPC for typical memory-device patterning processes for 3D mask
topographic effect. It is observed that this BLM successfully accounts for the 3D mask effect as reducing OPC model
error down to sub-50 nm node. BLM improves OPC-modeling accuracy depending on specific process conditions such
as mask type and pattern geometry. Potential limit of BLM, i.e., how accurately BLM could predict the 3D mask effect is
also investigated with respect to CD change: BLM also compared with rigorous simulation for various features and a
good match is obtained as small as below 0.5 nm. Some practical issue in OPC modeling such as determination of the
phase of boundary layer is addressed, which can be critical for prediction of defocus behavior.
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