Dr. Jeonghoon Lee Profile

Dr. Jeonghoon Lee

at imec

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Author

Publications (9)

Proceedings Article | 12 November 2024 Presentation + Paper

Logic and memory patterning breakthrough using High-NA lithography

V. Blanco Carballo, S. Roy, B. Chowrira, T. Pham, J. Wouters, S. Das, S. Decoster, P. Leray, R. Liu, K. Ronse, G. Vandenberghe, A. Niroomand, P. Foubert, V. Rutigliani, H. Suh, M. Gupta, D. de Simone, M. Dusa, C. Beral, V. Philipsen, V. Wiaux, J. Franke, J. Bekaert, B. Baskaran, W. Gillijns, R. Kim, Y. Sherazi, H. Vats, M. Cupak, C. Chang, Y.-J. Lin, J. Lee, S. Hwang, K. Yang, K. Miyaguchi

Proceedings Volume 13216, 1321604 (2024) https://doi.org/10.1117/12.3047176

KEYWORDS: Metals, Optical lithography, Logic, Semiconducting wafers, Extreme ultraviolet lithography, Etching, Scanning electron microscopy, Lithography, Tin

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Proceedings Article | 10 April 2024 Poster + Paper

Single mask solution to pattern DRAM LILP layer at 42nm pitch using EUV CAR photoresist

Arijit Das, Kiho Yang, Toto Chen, Pierce Chang, Sheng-Tse Chen, Shu-De Gong, Hyo Seon Suh, Jeonghoon Lee, Jan-Frederik Finoulst, Chris Wilson, Paulina Rincon Delgadillo, Murat Pak

Proceedings Volume PC12953, PC129530Z (2024) https://doi.org/10.1117/12.3011854

KEYWORDS: Critical dimension metrology, Extreme ultraviolet lithography, Optical lithography, Line width roughness, Photoresist materials, Semiconducting wafers, Finite element methods, Printing, Inspection, Cadmium

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Proceedings Article | 9 April 2024 Presentation + Paper

Patterning optimization for single mask bit-line-periphery and storage-node-landing-pad DRAM layers using 0.33NA EUV lithography at the resolution limit

Van Tuong Pham, Jeonghoon Lee, Kaushik Sah, Ying-Lin Chen, Seonggil Heo, Soobin Hwang, Kenichi Miyaguchi, Bappaditya Dey, Maria Chistiakova, Peter De Schepper, Philippe Bezard, Sara Paolillo, Danilo De Simone, Hyo Seon Suh, Victor Blanco

Proceedings Volume 12957, 129570V (2024) https://doi.org/10.1117/12.3010934

KEYWORDS: Printing, Extreme ultraviolet, Optical lithography, Etching, Extreme ultraviolet lithography, Design, Cadmium, Source mask optimization, Scanning electron microscopy, Semiconducting wafers

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Proceedings Article | 22 November 2023 Presentation

Single exposure EUV process optimization for SNLP and BLP layer for next-generation DRAM manufacturing

Andreia Santos, Jeonghoon Lee, Elke Caron, Syamashree Roy, Jelle Vandereyken, Masahiko Harumoto, Sandip Halder, Victor Blanco, Van Tuong Pham, Bappaditya Dey

Proceedings Volume PC12750, PC1275004 (2023) https://doi.org/10.1117/12.2687539

KEYWORDS: Error analysis, Defect detection, Manufacturing, Extreme ultraviolet lithography, Extreme ultraviolet, Thermal stability, Temperature control, Simulations, Scanning electron microscopy, Photovoltaics

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Proceedings Article | 28 April 2023 Presentation + Paper

Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning

Ana-Maria Armeanu, Evgeny Malankin, Neal Lafferty, Chih-I Wei, Monica Kempsell Sears, Germain Fenger, Xima Zhang, Werner Gillijns, Darko Trivkovic, Ryoung-han Kim, Jeonghoon Lee

Proceedings Volume 12495, 124950A (2023) https://doi.org/10.1117/12.2660413

KEYWORDS: Photomasks, Extreme ultraviolet, Source mask optimization, Resolution enhancement technologies, Optical proximity correction, Lithography, Optical lithography, Capacitors, Semiconducting wafers, SRAF

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Among several critical layers of DRAM (dynamic random-access memory), capacitor holes of honeycomb arrays and bit-line-periphery (BLP) with Storage Node Landing Pad (SNLP) are the most critical layers in terms of patterning difficulty level. The honeycomb array hole layer has the highest density among various hole array types, and it is a complex lithography step since this layer is key in determining the performance of the DRAM. BLP with SNLP includes hole type and bi-directional line/space (L/S) design, and industry is considering a single exposure solution, compared to a three-mask solution using ArF immersion [1]. This BLP layer of 10nm DRAM has 2 different types of pattern topologies, hole array and bi-direction line/space: it is a very challenging single exposure level. In this paper, we discuss patterning challenges that come as consequences of industry trends in DRAM cell size reduction [2,3]. To keep up with this trend and to propose a single mask solution for bit-line-periphery, storage node landing pads and aggressive cell array pitches are considered along with resolution enhancement techniques (RET) for high-NA anamorphic EUV (NA=0.55) lithography. This study uses computational lithography such as source mask optimization (SMO) to find optimal off-axis illumination and optimal placement of sub-resolution assist features (SRAF) on the mask whilst considering the manufacturing rules checks (MRC constraints) for anamorphic EUV masks. In order to achieve that, a screening Design Technology Co-optimization (DTCO) experiment is done. The purpose is to identify cell array pitches in between 24nm and 32nm which satisfy both scaling requirements and patterning fidelity, preferred orientation of layout, and mask biasing scheme for various cell arrays. Lithography metrics like common depth of focus (cDoF), exposure latitude (EL), image contrast, and image log slope (ILS) are used to decide what is optimal way to expose on wafer. For the sake of completeness of the study, mask materials are compared. Indeed, in EUV domain there is interest to use alternative mask absorbers like Ruthenium alloys as an alternative to Tantalum-based absorbers [4,5,6].

Proceedings Article | 28 April 2023 Paper

Patterning assessment using 0.33NA EUV single mask for next generation DRAM manufacturing

Jeonghoon Lee, Sandip Halder, Van Tuong Pham, Roberto Fallica, Seonggil Heo, Kaushik Sah, Hyo Seon Suh, Victor Blanco, Werner Gillijns, Andrew Cross, Ethan Maguire, Ana-Maria Armeanu, Vladislav Liubich, Evgeny Malankin, Xima Zhang, Monica Kempsell Sears, Neal Lafferty, Germain Fenger, Chih-I Wei, Ryoung Han Kim

Proceedings Volume 12495, 124950S (2023) https://doi.org/10.1117/12.2660763

KEYWORDS: Optical lithography, Extreme ultraviolet, Optical proximity correction, Design and modelling, SRAF, Semiconducting wafers, Inspection, Source mask optimization, Printing, Electronic design automation

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Proceedings Article | 1 December 2022 Poster + Paper

Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing

Kaushik Sah, Andrew Cross, Sayantan Das, Roberto Fallica, Jeonghoon Lee, Ryoung-Han Kim, Sandip Halder, Ethan Maguire, Ana-Maria Armeanu, Monica Sears, Neal Lafferty, Vlad Liubich, Chih-i Wei, Germain Fenger

Proceedings Volume 12292, 122920W (2022) https://doi.org/10.1117/12.2645953

KEYWORDS: Photomasks, Optical proximity correction, Stochastic processes, Extreme ultraviolet, Semiconducting wafers, Wafer-level optics, Source mask optimization, Manufacturing, Inspection, Signal to noise ratio, Defect inspection

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Proceedings Article | 26 May 2022 Paper

Orthogonal array pillar process development for high density 4F2 memory cells at 40nm pitch and beyond

Murat Pak, Wesley Zanders, Patrick Wong, Sandip Halder, Romuald Blanc, Laurent Souriau, Jeonghoon Lee, Gouri Sankar Kar

Proceedings Volume 12051, 120510J (2022) https://doi.org/10.1117/12.2618761

KEYWORDS: Semiconducting wafers, Photoresist materials, Array processing, Extreme ultraviolet lithography, Optical lithography, Finite element methods, Etching, Electroluminescence, Critical dimension metrology, Scanning electron microscopy

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Proceedings Article | 25 May 2022 Presentation + Paper

EUV based multi-patterning schemes for advanced DRAM nodes

Sayantan Das, Kaushik Sah, Roberto Fallica, Zhijin Chen, Sandip Halder, Andrew Cross, Danilo De Simone, Fergo Treska, Philippe Leray, Ryoung Han Kim, Ethan Maguire, Chih-I Wei, Germain Fenger, Neal Lafferty, Jeonghoon Lee

Proceedings Volume 12055, 1205503 (2022) https://doi.org/10.1117/12.2615644

KEYWORDS: Etching, Photomasks, Extreme ultraviolet, Optical lithography, Double patterning technology

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Showing 5 of 9 publications

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