It became more challenging to guarantee the overall mask Critical Dimension (CD) quality according to the increase of hot spots and assist features at leading edge devices. Therefore, mask CD correction methodology has been changing from the rule-based (and/or selective) correction to model-based MPC (Mask Process Correction) to compensate for the through-pitch linearity and hot spot CD errors.
In order to improve mask quality, it is required to have accurate MPC model which properly describes current mask fabrication process. There are limits on making and defining accurate MPC model because it is hard to know the actual CD trend such as CD linearity and through-pitch owing to the process dispersion and measurement error. To mitigate such noises, we normally measure several sites of each pattern types and then utilize the mean value of each measurement for MPC modeling. Through those procedures, the noise level of mask data will be reduced but it does not always guarantee improvement of model accuracy, even though measurement overhead is increasing. Root mean square (RMS) values which is usually used for accuracy indicator after modeling actually does not give any information on accuracy of MPC model since it is only related with data noise dispersion.
In this paper, we reversely approached to identify the model accuracy. We create the data regarded as actual CD trend and then create scattered data by adding controlled dispersion of denoting the process and measurement error to the data. Then we make MPC model based on the scattered data to examine how much the model is deviated from the actual CD trend, from which model accuracy can be investigated. It is believed that we can come up with appropriate method to define the reliability of MPC model developed for optimized process corrections.
Demand for mask process correction (MPC) is growing facing the 14nm era. We have developed model based MPC and can generate mask contours by using this mask process model. This mask process model consists of EB (development) and etch, which employs a threshold (level set) model and a variable bias model respectively. The model calibration tool accepts both CD measurement results and SEM images. The simulation can generate mask image (contour), runs with distributed computing resources, and has scalable performance.
The contour simulation shows the accuracy of the MPC correction visually and provides comprehensive information about hot spots in mask fabrication. Additionally, it is possible to improve lithography simulation quality by providing a simulated mask contour.
In this paper, accuracy and computational performance of mask process simulation are shown. The focus is on the difference between the calibration methods using CDs or images.
The increasing complexity of RET solutions has increased the shot count for advanced photomasks. In particular, the
introduction of the inverse lithography technique (ILT) brings a significant increase in mask complexity and
conventional fracturing algorithms generate many more shots because they are not optimized for curvilinear shapes.
Several methods have been proposed to reduce shot count for ILT photomasks. One of the stronger approaches is model-based
fracturing, which utilizes precise dose control, shot overlaps and many other techniques. However, it requires
much more computation resources and upgrades to the EB mask writer to support user-level dose modulation and shot
overlaps.
We proposed an efficient algorithm to fracture curvy shapes into VSB shots5 which was based on geometry processing.
The algorithm achieved better EPE and reasonable process time compared with a conventional fracturing algorithm but
its fracturing quality can be degraded for the pattern which has relatively rough contour though it is curvy ILT pattern.
In this paper, we present a couple of general techniques to refine a set of VSB shots to reduce edge placement error
(EPE) to an original curvy contour with their experimental results.
Computational lithography, e.g., inverse lithography technique (ILT) and source mask optimization, is considered necessary for the “extremely low k1” lithography process of sub-20 nm device node. The ideal design of a curvilinear mask for computational lithography requires many changes during photomask fabrication. These range from preparation of the mask data to measurement and inspection. The manufacturability of a photomask for computational lithography is linked to predictable and manageable quality of patterning. Here, we have proposed the use of “inverse e-beam lithography” on photomask for computational lithography, which overcomes the patterning accuracy limits of conventional e-beam lithography. Furthermore, the preferred target design for ILT, a new verification method, and the accuracy required for the mask model are also discussed; with consideration of acceptable writing time (<24 h ) and computing power.
The computational lithography such as inverse lithography technique (ILT) or source mask optimization (SMO) is considered as the necessary technique for the extremely low k1 lithography process of sub-20nm node. The ideal curvilinear mask design for computational lithography gives the impacts and requires many changes on the photomask fabrication from mask data preparation to measurement and inspection. In this paper, we present the current status and new requirements for the computational lithography mask in viewpoint of the manufacturability for mass production. The manufacturability of computational lithography mask can be realized by the predictable and manageable patterning quality. Here, we have proposed new data flow for ILT which covers what the preferred target design is for ILT, new verification method, required mask model accuracy, and resolution improvement method. Furthermore, considering acceptable writing time (<24 hours) and computation limit on convolution, the current ILT technique is shown to have the limit of application area.
Model-Based Mask Data Preparation (MB-MDP) has been discussed in the literature for its benefits in reducing mask
write times [1][2]. By being model based (i.e., simulation based), overlapping shots, per-shot dose modulation, and
circular and other character projection shots are enabled. This reduces variable shaped beam (VSB) shot count for
complex mask shapes, and particularly ideal ILT shapes [3]. In this paper, the authors discuss another even more
important aspect of MB-MDP. MB-MDP enhances CD Uniformity (CDU) on the mask, and therefore on the wafer.
Mask CDU is improved for sub-80nm features on mask through the natural increase in dose that overlapping provides,
and through per-shot dose modulation. The improvement in CDU is at the cost of some write times for the less complex
EUV masks with only rectangular features. But these masks do not have the basis of large write times that come from
complex SRAFs. For ArF masks for the critical layers at the 20nm logic node and below, complex SRAFs are
unavoidable. For these shapes, MB-MDP enhances CDU while simultaneously reducing write times. Simulated and
measured comparison of conventional methodology and MB-MDP methodology are presented.
Mask Error Enhancement Factor (MEEF) has been a standard measure of mask quality [1]. One of the key
assumptions in the construction of MEEF is that mask CD uniformity is not dependent on the shape of mask
feature and can be considered to be a constant for given mask process. This assumption is no longer valid for
small (<100nm), curvilinear or diagonal features. In this paper we extend definition of MEEF to be valid for all
mask shapes call new metric extended MEEF or eMEEF. We also demonstrate on the example of ILT features that
eMEEF increases predictability of mask and wafer CD uniformity sometimes changing overall conclusion about
mask/wafer manufacturability.
In the IC process, the designed circuit pattern is drawn onto film or glass plate as a photo mask. This original mask is used to transform its transparent pattern onto semiconductor wafers by optical projection. To make photo mask we should convert the design data into a format that the e-beam write tool can understand. This MDP (Mask Data Preparation) process is getting more and more complicated to support many kinds of e-beam data format which is required not only for each electron beam writers but die to database inspection tools. It gives us a burden to treat various MDP flow and this may impact on turn around time (TAT). Therefore, it becomes more necessary to make MDP flow simpler by unifying the various mask data formats. Moreover it is required to suppress huge data volume due to design rule shrink and aggressive OPC. To address these issues, the Open Artwork System Interchange Standard (OASISTM) has been approved by the EDA industry and is officially announced by SEMI Data Path Task Force. OASIS data format allows the reduction in file size compared to GDSII while the processing time such as MRC and MDP is not influenced. Also OASIS is effective in reducing complexity of mask data preparation flow. In this paper, the implementation of OASIS format within mask data preparation flow will be discussed and experimental results of OASIS-based data flow will be shown with comparing to traditional GDSII/MEBES-based data flow.
As the design rule with wafer is tightening to sub-100nm, the specification of Mask CD uniformity is steeply tightened too. For instance, according to 2004 ITRS Roadmap updated, the specification of DRAM's CD uniformity requires less then 7nm on 80nm nodes in Yr. 2005. In order to satisfy that specification, it is important to analyze various factors such as e-beam machine error, heating effect, fogging effect, proximity effect, and process errors which cause CD non-uniformity in the mask.
In this paper, a simulation method will be introduced to calculate the local and global heating effect by applying DP(Distributed Processing). First, experiments were performed to see heating effects on mask CD uniformity. In case of the ZEP process with 50KeV exposure, the CD error caused by heating effect amounted to 45nm in worst case. Second, heating effect was simulated using DP. Recently, most simulators have been required high accuracy. However, it is inevitable to spend more calculation time. To improve that problem, DP has been adopted in many softwares. In this paper, MPI(Message Passing Interface) library was applied to simulate heating effect. Finally, the experiment and simulated results were compared. As a result, simulation results could explain the CD errors investigated on our experiment. In our experiment, 2D simulation is sufficient to expect CD errors caused by resist heating effect.
As a promising technology for sub-65nm node optical lithography, CLM(Chrome-Less Mask) technology among RETs(Resolution Enhancement Techniques) for low k1 has been researched worldwide in recent years. CLM has several advantages, such as relatively simple manufacturing process and competitive performance compared to phase-edge PSM's. For the low-k1 lithography, we have researched CLM technique as a good solution especially for sub-65nm node.
As a step for developing the sub-65nm node optical lithography, we have applied CLM technology in 80nm-node lithography with mesa and trench method. From the analysis of the CLM technology in the 80nm lithography, we found that there is the optimal shutter size for best performance in the technique, the increment of wafer ADI CD varied with pattern's pitch, and a limitation in patterning various shapes and size by OPC dead-zone - OPC dead-zone in CLM technique is the specific region of shutter size that dose not make the wafer CD increased more than a specific size. And also small patterns are easily broken, while fabricating the CLM mask in mesa method. Generally, trench method has better optical performance than mesa. These issues have so far restricted the application of CLM technology to a small field.
We approached these issues with 3-D topographic simulation tool and found that the issues could be overcome by applying phase grating in trench-type CLM. With the simulation data, we made some test masks which had many kinds of patterns with many different conditions and analyzed their performance through AIMS fab 193 and exposure on wafer.
Finally, we have developed the CLM technology which is free of OPC dead-zone and pattern broken in fabrication process. Therefore, we can apply the CLM technique into sub-65nm node optical lithography including logic devices.
In the ArF lithography for sub-100nm, PSM (Phase Shift Mask) has been considered as one of the basic RETs (Resolution Enhancement Techniques). Nowadays, besides attenuated PSM, alternating PSM and CPL (Chromeless Phase Lithography) containing Cr patch is widely studied for targeting sub-100nm. Since 2nd process using 365nm laser tools for Cr patch has been a wide gap between the reality and the demands, various candidates using 254nm laser or e-beam exposure tool have been presented to overcome the current 2nd process limitation. And, the Cr patch operate as an assist pattern to control the transmittance of mask, therefore, the CPL mask with Cr patch have advantages of improving process margin such as dose margin and its applicable flexibility for various layers, dense or isolated pattern in the memory and logic device. In this paper, we scrutinize the feasibility of 2nd alignment using 10keV e-beam. Process issues such as the charging effects caused by 2nd e-beam exposure on the 1st Cr etched substrate were evaluated as well.
High speed circuit usually requires additional gate scaling regardless of its developed technology node. In this paper, we demonstrate the full-chip-level wafer result for 100nm node SRAM gate and the possibility of future gate scaling. Test reticle is manufactured using chromeless phase lithography(CPL). CPL technology uses a COG that consists of p -phased-etched quartz and chrome shield for various gate CD formation. Critical transistor area is 100% transmission PSM. However, less-critical area should be a chrome for adequate CD control. Because light interference is weakened in phase area according to the separation of paired phase edges increase. The optical performance and manufacturing issues of CPL are evaluated compared to other PSM technologies. Finally, we describe how to optimize the CPL mask using simulation and wafer analysis to obtain the acceptable OCV and DOF margin for volume production.
As semiconductor devices are scaled down to the sub-100nm node, the fine control of ACLV (across-chip line-width variation) to improve the performance of chips and the expansion of the process window to enhance yield are required. One of the techniques reducing ACLV is MPPC (model-based process proximity correction). However, it increases pattern complexity and does not guarantee enough process windows. Therefore, we propose a HPPC (hybrid PPC) methodology combining RPPC (rule-based PPC) and MPPC, which correct the gate on active by MPPC for device performance and the field gate by RPPC for process window. In addition, we optimize SRAF (sub-resolution assist feature) design to improve process windows further at the full chip level and apply the multi-step correction, which corrects optical and etch proximity effects separately to minimize ACLV. As the result of the application to the 90nm logic gate, we achieve over 0.3um DOF (depth of focus) and the line-width variation within ±5% of the target CD (critical dimension).
Chrome Less phase lithography (CPL) may be the crucial technology to print 100nm node and below. CPL can apply to various design layers without causing phase conflicts, while phase edge phase shift mask (PEPSM) is beneficial for specific pattern configurations and pitches. Therefore, we tested the feasibility of CPL including phase grating and hybrid CPL. And we tested the two types of CPL such as mesa and trench structures to decide the proper shifter forming method. We evaluated pattern fidelity of CPL using simulation, aerial image measurement system (AIMS) and wafer printing. Finally, we will compare the optical performance between CPL and PEPSM for 100nm node SRAM gate.
In the exponential drive to go to the smaller feature size, the control of the line width variation becomes more important than ever before. Hybrid PPC (Process Proximity Correction) has been one of the indispensable methods to satisfy the requirements of CD control and yield improvement. In this paper, an effective methodology for hybrid PPC is presented to reduce the data volume and the complexity of patterns and to enhance the accuracy of correction. The selective engine in the hybrid PPC flow classifies the gate patterns into the areas of model-based and rule-based PPC considering a device performance, a modeling accuracy, and the extension of the contact overlap margin. The effective method of edge pattern modeling is exploited to compensate the nonlinear etch proximity effect in the asymmetrical pattern configuration. Using the hybrid PPC method with the 1 nm correction grid, 22% of the additional reduction in the intra-die CD variation compared to the rule-based PPC with 5 nm correction grid has been achieved.
Insufficient metal overlaps over contacts and/or vias impact serious yield loss especially in the borderless-contact- style random logic devices. Vias which are not fully covered by interconnects cause not only the functional error due to the high via resistance but also the reliability problem such as electro migration. It is not sufficient to compensate only optical proximity effects such as line-end shortening and corner rounding for the overlap margin. Since mis-alignment between interconnects and over/underlying features is not negligible even using an advanced alignment system of step and scanner. Therefore, the need for aggressive OPC is increased to cope with the proximity effect and overlay error in metal interconnects. The proposed OPC approach gives a robust metal overlap with fast runtime and allowable data complexity by selective correction for the improperly overlapped contacts and vias. Experimental results for the test design show that the correction time of the metal interconnects takes 11 hours at HP5600 system by applying the proposed correction algorithm.
In this paper, we report highly effective Optical Proximity Correction (OPC) techniques to improve the process margin in the photo lithography process of metal layer, which can be applied to 0.14 micrometer DRAM technology node and beyond. The proposed test pattern reflects the optical limitation of each situation, the rules can be established by simply investigating the test patterns which solves the problems such as lack of contact overlap margin, line-end shortening, and size reduction in isolated and island patterns. This sophisticated rule is considering the vertical environment as well. Thanks to systematic sequence for rule extraction, we could minimize additional burdens such as error occurrence, rule set-up time, data volume, manufacturing time of mask. By applying this method, DOF margin of metal layer could be improved from 0.4 micrometer to beyond 0.6 micrometer, which provides sufficient process window for mass production of 0.14 micrometer DRAM technology. In addition, we also confirmed that the new OPC technology could be extended to the metal layer of 0.11 micrometer DRAM.
A practical optical proximity correction (OPC) method is introduced and applied to 0.25 micrometers DRAM process in order to reduce the gate critical dimension (CD) variations across the exposure field. A variable threshold model is made and evaluated to enhance the model accuracy. This model takes maximum 2X computation time compared with the constant threshold model. The proposed OPC methodology considering both process effects and mask manufacturability simultaneously is discussed in view of the gate line CD variation. The correction segments of a pattern are optimized considering mask manufacturability. Patterns with jog sizes larger than 0.4 micrometers are inspect able with KLA35UV. The OPC results exhibited 60 percent reduction of gate CD variation, 90 percent matching of mean-to-target CD, and 15 percent improvement of circuit performance.
This paper present a systematic approach to correct critical patterns, which are more prone to defects due to the photo lithography process, at the full-chip level for sub-quarter micron CMOS applications. In the first stage of the photo lithography process for integrated circuits (IC), the bridging failure between patterns in a photoresist layer has been found occasionally. The small process margin in patterning plays a key part of the device yield drop, when process conditions or production lines are changed. However, it is a very difficult and time-consuming job to find and correct all the possible critical patterns which might cause failure. Test patterns with various line-and-spaces are designed and simulated using the aerial image model and the third order polynomial function of critical patterns. The DRC software with the rules searches an entire area of the IC layout. The proposed approach to extract critical patterns is cost effective and fast compared to the evaluation of a layout using a photo lithography simulator at the full-chip level. Applying this methodology to 256M DRAM with 0.25 micrometers minimum design width in the periphery and core area, all bridge defects found before correction can be removed. Furthermore, it will be a useful tool to the product engineer who should indicate monitoring patterns, which are sensitive to the lithography process margin.
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