Dr. Juan-Manuel Gomez Profile

Dr. Juan-Manuel Gomez

at IBM Thomas J Watson Research Ctr

SPIE Involvement:

Author

Publications (13)

Proceedings Article | 10 April 2024 Presentation

Controlling patterning uniformity in thick resist lithography

Christopher Bottoms, Alexander Hamer, Alejandro Mejia, Alex Hubbard, Nicholas Latham, Katherine Sieg, Jennifer Fullam, Vinay Pai, Junwon Han, Juan-Manuel Gomez, Christopher Waskiewicz, Shahid Butt

Proceedings Volume PC12956, PC129560E (2024) https://doi.org/10.1117/12.3012541

KEYWORDS: Optical lithography, Lithography, Coating thickness, Semiconducting wafers, Plating, Photoresist processing, Dielectrics, Coating

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Proceedings Article | 20 March 2018 Presentation + Paper

Overlay control for 7nm technology node and beyond

Nyan Aung, Woong Jae Chung, Pavan Samudrala, Haiyong Gao, Wenle Gao, Darius Brown, Guanchen He, Bono Park, Michael Hsieh, Xueli Hao, Yen-Jen Chen, Yue Zhou, DeNeil Park, Karsten Gutjahr, Ian Krumanocker, Kevin Jock, Juan Manuel Gomez

Proceedings Volume 10587, 105870A (2018) https://doi.org/10.1117/12.2295828

KEYWORDS: Overlay metrology, Semiconducting wafers, Optical alignment, Reticles, High volume manufacturing, Metrology, HVAC controls, Optimization (mathematics), Scanners, Extreme ultraviolet

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Proceedings Article | 28 March 2017 Paper

Enhanced methodology of focus control and monitoring on scanner tool

Yen-Jen Chen, Young Ki Kim, Xueli Hao, Juan-Manuel Gomez, Ye Tian, Ferhad Kamalizadeh, Justin Hanson

Proceedings Volume 10145, 101452K (2017) https://doi.org/10.1117/12.2258125

KEYWORDS: Scanners, Diffraction, Metrology, Semiconducting wafers, Process control, Calibration, Reticles, Overlay metrology, Critical dimension metrology, Lithography

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As the demand of the technology node shrinks from 14nm to 7nm, the reliability of tool monitoring techniques in advanced semiconductor fabs to achieve high yield and quality becomes more critical. Tool health monitoring methods involve periodic sampling of moderately processed test wafers to detect for particles, defects, and tool stability in order to ensure proper tool health. For lithography TWINSCAN scanner tools, the requirements for overlay stability and focus control are very strict. Current scanner tool health monitoring methods include running BaseLiner to ensure proper tool stability on a periodic basis. The focus measurement on YIELDSTAR by real-time or library-based reconstruction of critical dimensions (CD) and side wall angle (SWA) has been demonstrated as an accurate metrology input to the control loop. The high accuracy and repeatability of the YIELDSTAR focus measurement provides a common reference of scanner setup and user process. In order to further improve the metrology and matching performance, Diffraction Based Focus (DBF) metrology enabling accurate, fast, and non-destructive focus acquisition, has been successfully utilized for focus monitoring/control of TWINSCAN NXT immersion scanners. The optimal DBF target was determined to have minimized dose crosstalk, dynamic precision, set-get residual, and lens aberration sensitivity. By exploiting this new measurement target design, ~80% improvement in tool-to-tool matching, >16% improvement in run-to-run mean focus stability, and >32% improvement in focus uniformity have been demonstrated compared to the previous BaseLiner methodology. Matching <2.4 nm across multiple NXT immersion scanners has been achieved with the new methodology of set baseline reference. This baseline technique, with either conventional BaseLiner low numerical aperture (NA=1.20) mode or advanced illumination high NA mode (NA=1.35), has also been evaluated to have consistent performance. This enhanced methodology of focus control and monitoring on multiple illumination conditions, opens an avenue to significantly reduce Focus-Exposure Matrix (FEM) wafer exposure for new product/layer best focus (BF) setup.

Proceedings Article | 21 April 2016 Paper

Analysis of wafer heating in 14nm DUV layers

Lokesh Subramany, Woong Jae Chung, Pavan Samudrala, Haiyong Gao, Nyan Aung, Juan Manuel Gomez, Blandine Minghetti, Shawn Lee

Proceedings Volume 9778, 97780U (2016) https://doi.org/10.1117/12.2218724

KEYWORDS: Semiconducting wafers, Overlay metrology, Deep ultraviolet, Scanners, Process control, Photomasks, Reticles, Metrology, Metals, Data modeling, Image enhancement

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Proceedings Article | 24 March 2016 Paper

Focus control enhancement and on-product focus response analysis methodology

Young Ki Kim, Yen-Jen Chen, Xueli Hao, Pavan Samudrala, Juan-Manuel Gomez, Mark Mahoney, Ferhad Kamalizadeh, Justin Hanson, Shawn Lee, Ye Tian

Proceedings Volume 9778, 97780T (2016) https://doi.org/10.1117/12.2213019

KEYWORDS: Error analysis, High volume manufacturing, Semiconducting wafers, Metrology, Process control, Control systems, Scanners, Diffraction, Time metrology, Forward error correction, Lithography, Critical dimension metrology

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Proceedings Article | 18 March 2016 Paper

Advanced overlay: sampling and modeling for optimized run-to-run control

Lokesh Subramany, WoongJae Chung, Pavan Samudrala, Haiyong Gao, Nyan Aung, Juan Manuel Gomez, Karsten Gutjahr, DongSuk Park, Patrick Snow, Miguel Garcia-Medina, Lipkong Yap, Onur Nihat Demirer, Bill Pierson, John Robinson

Proceedings Volume 9778, 97782K (2016) https://doi.org/10.1117/12.2218729

KEYWORDS: Semiconducting wafers, Data modeling, Overlay metrology, Metrology, Process control, Scanners, Mathematical modeling, High volume manufacturing

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In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the “sample plan” of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

Proceedings Article | 15 March 2016 Paper

CDU budget breakdown as a diagnostic method for imaging sensitivity in HVM

Young Ki Kim, Pavan Samudrala, Juan-Manuel Gomez, Peter Nikolsky, Roy Anunciado, Maria Barkelid, Shawn Lee, Ye Tian, Justin Hanson

Proceedings Volume 9780, 97801Q (2016) https://doi.org/10.1117/12.2214123

KEYWORDS: Semiconducting wafers, Reticles, Critical dimension metrology, Scanners, Photomasks, Metrology, Laser processing, Laser scanners, 3D scanning, Laser metrology

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Proceedings Article | 8 March 2016 Paper

Scanner baseliner monitoring and control in high volume manufacturing

Pavan Samudrala, Woong Jae Chung, Nyan Aung, Lokesh Subramany, Haiyong Gao, Juan-Manuel Gomez

Proceedings Volume 9778, 977838 (2016) https://doi.org/10.1117/12.2218162

KEYWORDS: Overlay metrology, Scanners, Data modeling, High volume manufacturing, Process control, Manufacturing, Performance modeling, Metrology, Statistical modeling

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Proceedings Article | 8 March 2016 Paper

Comparison study of diffraction based overlay and image based overlay measurements on programmed overlay errors

Haiyong Gao, Woong Jae Chung, Nyan Aung, Lokesh Subramany, Pavan Samudrala, Juan-Manuel Gomez

Proceedings Volume 9778, 97782Q (2016) https://doi.org/10.1117/12.2218163

KEYWORDS: Overlay metrology, Metrology, Diffraction, Process control, Lithography, Semiconductor manufacturing, Error analysis, Reticles, Semiconducting wafers

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Proceedings Article | 8 March 2016 Paper

Overlay optimization for 1x node technology and beyond via rule based sparse sampling

Nyan Aung, Woong Jae Chung, Lokesh Subramany, Shehzeen Hussain, Pavan Samudrala, Haiyong Gao, Xueli Hao, Yen-Jen Chen, Juan-Manuel Gomez

Proceedings Volume 9778, 97782G (2016) https://doi.org/10.1117/12.2218161

KEYWORDS: Overlay metrology, Metrology, Process control, Statistical modeling, Semiconducting wafers, Scanners, Data centers, MATLAB, Manganese, Semiconductor manufacturing, High volume manufacturing

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Proceedings Article | 16 April 2011 Paper

Critical challenges for non-critical layers

J. M. Gomez, I. Popova, B. Zhang, H. Kry, S. Holmes, S. Nakagawa, T. Murakami, Chan Sam Chang, Cheol Kim

Proceedings Volume 7972, 79722T (2011) https://doi.org/10.1117/12.879866

KEYWORDS: Photoresist processing, Lithography, Germanium, Photomasks, Semiconducting wafers, Critical dimension metrology, Tolerancing, Reflectivity, Etching, Scanners

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Proceedings Article | 1 April 2009 Paper

Message to the undecided: using DUV dBARC for 32-nm node implants

Hyung-Rae Lee, Irene Popova, JoAnn Rolick, Juan-Manuel Gomez, Todd Bailey

Proceedings Volume 7273, 72730Y (2009) https://doi.org/10.1117/12.814269

KEYWORDS: Photoresist processing, Semiconducting wafers, Reflectivity, Optical proximity correction, Lithography, Photomasks, Line edge roughness, Process control, Critical dimension metrology, Etching

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In recent years, implant (block) level lithography has been transformed from being widely viewed as non-critical into one of the forefronts of material development. Ever-increasing list of substrates, coatings and films in the underlying stack clearly dictates the need for new materials and increased attention to this challenging area. Control of the substrate reflectivity and critical dimension (CD) on topography has become one of the key challenges for block level lithography and is required in order to meet their aggressive requirements for developing 32nm technology and beyond. The simulation results of wet-developable bottom anti-reflective coating (dBARC) show better reflectivity control on topography than the conventional top anti-reflective materials (TARCs), and make a convincing statement as to viability of dBARC as a working solution for block level lithography.1 Wet-developable BARC by definition offers substrate reflectivity and resist adhesion control, however there is a need to better understand the fundamental limitations of the dBARC process in comparison to the TARC process. In addition, some specific niche dBARC applications as facilitating adhesion to challenging substrates, such as capping layers in the high-k metal gate (HK/MG) stack, can also be envisioned as most imminent dBARC applications.2 However, most of the engineering community is still indecisive to use dBARC in production, bound by uncertainties of the robustness and lack of experience using dBARC in production. This work is designed to inspire more confidence in the potential use of this technology. Its objective is to describe testing of one of dBARC materials, which is not a photosensitive type, and its implementation on 32nm logic devices. The comparison between dBARC and TARC processes evaluates impacts of dBARC use in the lithographic process, with special attention to OPC behavior and reflectivity for controlling CD uniformity. This work also shows advantages and future challenges of dBARC process with several 248nm and 193nm resists on integrated wafers, which have shallow trench isolation (STI) and poly gate pattern topography.

Proceedings Article | 15 March 2006 Paper

Immersion lithography robustness for the C065 node

Scott Warrick, Rob Morton, Andrea Mauri, Jean-Damien Chapon, Jerome Belledent, Will Conley, Alex Barr, Kevin Lucas, Cedric Monget, Valerie Plantier, David Cruau, Juan-Manuel Gomez, Emmanuel Sicurani, Jan-Willem Gemmink

Proceedings Volume 6154, 615407 (2006) https://doi.org/10.1117/12.657158

KEYWORDS: Optical proximity correction, Immersion lithography, Semiconducting wafers, Scanners, Etching, Line width roughness, Manufacturing, Optical lithography, Lithography, Metals

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Semiconductor manufacturers are in the midst of the next technology node C045 (65nm half-pitch) development. The difference this time is that the heavy lifting is being done while swimming. Generally, for the C065 node (hp90), critical layers will be processed using 193-nm scanners with numerical apertures up to 0.85. It is also clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) should to be examined, in addition to the development of immersion lithography for the C045 and C032 technology generations. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. A strategy of replacing conventional "dry" lithographic process steps with immersion lithographic process steps would allow the benefits of immersion to be realized much earlier. To fully realize this advantage a direct comparison of immersion lithography's benefits and therefore speed learning is needed. However, such an insertion should be "transparent": i.e. the "immersion process" should run with the same reticles (OPC) and resists, as the conventional process. In an effort to gain this knowledge about the immersion processes, we have chosen a path of optimizing and ramping-up the lithographic process for the C065 technology node. In this paper, we report on the compatibility of inserting immersion lithography processes into an established C065 process running in a pilot manufacturing line. We will present an initial assessment of some critical parameters for the implementation of immersion lithography. This assessment includes: OPC compatibility, imaging, process integration, and defectivity all compared to the dry process of record. Finally, conclusions will be made as to the overall readiness of immersion to support C065 node processing in direct transfer from dry and its extendibility to C045. In this work, the C045 technology node (hp65) is the main target vehicle. However, a successful introduction of immersion technology may allow a strategy change complementary with the previous (C065) technology node (i.e. run C065 immersion in production and benefit from larger process windows).

Showing 5 of 13 publications

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