Traditional modeling of computational lithography starts first by determining the functional relationship between the change in focus and the aerial image (AI) location of the optical model by setting constraints and then calibrating the resist model separately. In this process, built-in genetic algorithm (GA) tools usually participate in the parameter optimization process of only one model at a time. Additionally, GA tools are vulnerable to becoming trapped in a locally optimal solution. The practice of optimizing the optical and resist models separately may potentially miss better solutions. We propose a method to co-optimize the two models simultaneously. This is done by finding the Pareto optimal frontier of potentially better solution candidates that balance these two models. To avoid the local optimal solution trap, a method is proposed to increase the search range when the algorithm is confined. In the selecting and scoring models process, we quantify metrics that are typically made empirically by engineers to achieve higher levels of automation.
Resist reflow techniques have widely been adopted for lithography in resolution limited region. During the reflow process, resist patterns are heated over its glass temperature through number of temperature steps. Early works have focused how the temperature steps during heat-up process can be effectively controlled for critical dimension (CD) and the pattern profile after reflow. However, for a specific application that needs moderate CD and profile change, adjusting heat-up parameters would not be sufficient to achieve good CD and profile control and additional relevant parameters should be accounted.
In this paper, we count surface treatment condition on reflow process as an additional control parameter. We measured CDs with varying surface treatment parameters of substrate on square arrays of resist islands with 300 nm island-to-island gap space. We found that the amount of after develop CD to after reflow CD bias decreases as contact angles of substrates increases. In conclusion, we prove the resist reflow CD can be controlled precisely by adjusting the substrate coverage of hydroxyl groups during adhesion treatments in addition to the temperatures for the resist reflow process.
We discussed to KrF process extension for 90 nm technology node. The continuous shrinkage of critical dimensions on
sub 130 nm devices becomes a key point to improve process margin with pattern resolution problem for lithography.
Recently, according to development demand of high density and high integration device, it is tendency that the shrink
rate of design rule is gradually accelerated. It is difficult to develop with image contrast problem around k1=0.25 which
is a theoretical process limit region. We need to technology development which is available to having resolution for sub
90nm line and space by using KrF lithography not by using ArF lithography.
In generally, KrF have not been used in nano-process such as 90nm technology. In this study, however, we can apply
the KrF in 90nm technology by means of minimizing the error range in the nano-process, optimizing the process, and
extending the process margin. This Application of KrF in 90nm technology results in elimination of additional
investment for development of 90nm technology.
Finally, we will show which simulation and experimental results such as normalized image log slope, pupil plane,
image of focus variation, process window, top view image, photo resist and etch profile, and pitch linearity.
As semiconductor technologies move toward 90nm generation and below, contact hole is one of the most challenging
features to print in the semiconductor manufacturing process. There are two principal difficulties in order to define small
contact hole pattern on wafer. One is insufficient process margin besides poor resolution compared with line & space
pattern. The other is that contact hole should be made through pitches and sometimes random contact hole pattern should
be fabricated. Therefore advanced ArF lithography scanner should be used for small contact hole printing with RETs
(Resolution Enhancement Techniques) such as immersion lithography, OPC(Optical Proximity Correction), PSM(Phase
Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant Feature), mask
biasing and thermal flow. Like this, ArF lithography propose the method of enhancing resolution, however, we must
spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF.
In this paper, we suggest the method of contact holes patterning by using KrF lithography tool in 90nm sFlash(stand
alone Flash)devices. For patterning of contact hole, we apply RETs which combine OAI and Model based OPC.
Additionally, in this paper we present the result of hole pattern images which operate ArF lithography equipment. Also,
this study describes comparison of two wafer images that ArF lithography process which is used mask biasing and Rule
based OPC, KrF lithography process which is applied hybrid OPC.
Flare is unwanted light arriving at the wafer and light causing negative impact on pattern formation. It is caused
by scattered light from lens surfaces, problem on lens design, or problem on lens manufacture. The impact of flare varies
printed line widths or drops CD uniformity accuracy in full chip. And, It is an added incoherent background intensity that
will degrade OPC(Optical Proximity Correction) accuracy[1].
In this paper, we discussed CD variation, MEEF (Mask Error Enhancement Factor) and OPC accuracy by the
flare effects. Flare is bound up with local pattern density. Local pattern density influences background intensity by flare
or stray light. So we studied CD variation, MEEF, OPC modeling data with local pattern density by several experiment.
Also, in this study, we will discuss test pattern drawing for OPC modeling data, analyze CD difference between OPC test
pattern with considering flare effect and test pattern with regardless flare effect and MEEF value by flare effect. MEEF is
main factor that influences lithography process margin. This paper will show test pattern optimization in OPC modeling.
In low-k1 imaging lithography process it is difficult to make the accurate OPC model not only because of factors caused
by unstable process such as large CD (Critical Dimension) variation, large MEEF (Mask Error Enhancement Factor) and very poor process window but also because of potential error factors induced during OPC model fitting. In order to minimize those issues it is important to reduce the errors during OPC modeling. In this study, we have investigated the most influencing error factors in OPC modeling. At first, through comparing influence of optical parameters and illumination systems on OPC runtime and model accuracy, we observe main error factor. Secondly, in the case of resist modeling, OPC runtime and model accuracy were also analyzed by various model forms.
The methodology of lithography friendly design (LFD) has been widely adopted since it dramatically reduces cycle of
design revision as well as number of learning cycles to reach acceptable yield. LFD is, for example, the reduction
number of small jogs and notches in original, pre-OPC layouts. We can call them as OPC-unfriendly patterns since they
create unnecessarily complicated OPC patterns. They usually meet design rule so that DRC does not detect or screen
them out. Also, they make many errors after OPC because OPC model recognizes just as one of small features that it
should care. This generates many false alarms at OPC verification and mask rule check.
General approach to implement LFD is to update rule table or design rule by taking actual yield and failure analysis
data into consideration of database handling flow. Another method is the utilization of simulation to predict lithography
unfriendly designs. It takes time to setup excellent rule for accurate prediction even if they are very good approach as
fundamental solution for LFD. It will be better to have a simple solution with fast setup and improvement on major
lithography unfriendly designs such as small jogs and notches.
In this paper, we proposed new type of LFD flow which is the application of modified DRC step on LFD flow. This
modified DRC identifies OPC-unfriendly patterns, and changes to "OPC-friendly" as well as fixing design rule
violations. It is a pre-OPC layout treatment to remove small jogs and notches. After finding small jogs or notches, DRC
software removes jogs and notches. In this case, unnecessary OPC fragments could be avoided. Using this jog-fill
technique, we can dramatically reduce the incidence of necking or bridging, improve contact coverage, and, as a result, it
enhances the final yield and reliability of circuit.
KEYWORDS: Photoresist materials, Line edge roughness, Temperature metrology, Etching, Optical lithography, Scanning electron microscopy, Diffusion, Lithography, Reflectivity, Process control
In this study, we have investigated the profile of ArF photo-resist patterns in order to optimize the next generation
photo process of trench layer and improve their profile. In terms of resolution, PR (Photo Resist) for 193 nm (ArF) has
better quality than that of 248 nm (KrF). However, there found some problems such as LER (Line Edge Roughness), top
loss, sloped side wall, footing and standing wave in the aspect of PR profile. Thus, we observed the ArF PR profile
which has different process condition like TBARC, SOB (Soft Bake) and PEB (Post Exposure Bake) for the profile
optimization. As a result, the enhancement of sloped side wall, footing, and rounded top is obtained when the SOB and
PEB temperature are tuned under the optimized condition of TBARC (BARC thickness), and TPR (PR thickness). Finally,
we could set up the optimized process condition according to the result described above.
In lithography process, resolution enhancement technique (RET) which makes us use same lithographic
equipments and materials is one of most important area to enhance development speed of device. The studies for RET
have widely been done and the examples of RET are modified illumination, phase shifted mask and double exposure.
The most studies have been done in lithography area. We think that area of RET study is not only lithography but also
overall patterning including etching process.
In this paper, we develop new RET and simultaneous patterning of Shallow Trench Isolation(STI) with gate
pattern which is using oxidation process of silicone. When we use nitride hard mask process and etching with this
oxidation process, we observed to achieve small resolution. Also we investigate process capability of this new process in
terms of CD control, STI height and so on.
In resolution limited lithography process, the image deformation is getting severer. This is very important area where
we need to fully understand and improved since the image deformation is directly giving poor CD control effect.
Especially, contact hole image will be more sensitive since it has lower k1 factor that line and spaced pattern. This image
deformation of contact hole can give some severe electrical fail due to not opened contact. In our case, we observed
some critical failure mode of diagonal induced by abnormal contact hole shape of rough edge.
In this paper, we investigate how deformed contact hole image impacted on degradation of device performance in
electrical properties and yield and how we can improve it. To quantitatively analyze image deformation of contact hole,
we recommend new measurement method first. This new measurement gives exact image deformation amount at
different experimental conditions.
Finally, we will show how experimental conditions such as soft bake temperature, post expose bake temperature,
hardening bake temperature, illumination condition and mask bias change image deformation of contact hole.
As the resolution requirement downing 90 nm beyond, hole pattern is one of the most challenging features to print in
the semiconductor manufacturing process. Especially, when hole patterns have dense array of holes as they are consisted
of several columns with single row, there can be serious distorted form from desired patterns such as oval hole shape and
bridge between holes. It is due to nature of diffraction which generates interaction of diffracted light from near holes.
Overlap margin reduction by hole shape change as oval shape is very harmful in sub-90nm photolithography process
which has very narrow overlay margin. To increase overlap margin, it is necessary to solve these phenomenon. Optical
Proximity Correction (OPC) has been used for overcoming oval hole shape. Through the result of OPC modeling and
simulation, we could get optimized mask bias of hole. Sometimes, good experimental data will be help for this modeling
and OPC process. From these OPC simulation and experimental data, most compatible rule based OPC process could be
developed. In this paper, we suggest the method of improving oval hole shape by using OPC simulation and making rule
base OPC process from experimental data.
For the 90nm node and beyond, smaller Critical Dimension(CD) control budget is required and the ways to control good
CD uniformity are needed. Moreover Optical Proximity Correction(OPC) for the sub-90nm node demands more accurate
wafer CD data in order to improve accuracy of OPC model. Scanning Electron Microscope (SEM) is the typical method
for measuring CD until ArF process. However SEM can give serious attack such as shrinkage of Photo Resist(PR) by
burning of weak chemical structure of ArF PR due to high energy electron beam. In fact about 5nm CD narrowing occur
when we measure CD by using CD-SEM in ArF photo process. Optical CD Metrology(OCD) and Atomic Force
Microscopy(AFM) has been considered to the method for measuring CD without attack of organic materials. Also the
OCD and AFM measurement system have the merits of speed, easiness and accurate data. For model-based OPC, the
model is generated using CD data of test patterns transferred onto the wafer. In this study we discuss to generate accurate
OPC model using OCD and AFM measurement system.
The continuous shrinkage of critical dimensions has driven ArF lithography to resolve very small features and ever
thinner resist films to prevent pattern collapse. Also importance of hardmask technology is becoming increasingly
evident as the demand for both the critical dimension control and sufficient thickness of etch mask.
We have developed a silicon based hardmask prepared by plasma-enhanced chemical vapor deposition (PECVD) to
match organic anti-reflective coating (ARC). The ordinary single dielectric ARC or organic ARC is very sensitivity to the
substrate topology. Dual ARC (dielectric ARC + organic ARC) perform a less CD variation than single ARC. In addition,
this material can serve as an effective hardmask etch barrier during the plasma etch.
The most advantage of Dual ARC is that we have good critical dimension uniformity (CDU) regardless of substrate
thickness variation.
KEYWORDS: Data modeling, Optical proximity correction, Data conversion, Process modeling, Critical dimension metrology, Reactive ion etching, Scanning electron microscopy, Photomasks, Etching, Image processing
OPC has become an indispensable tool used in deep sub-wavelength lithograph process enabling highly accurate CD
(Critical Dimension) control as design rule shrinks. Rule based OPC was widely acceptable in the past, however it has
recently turned toward model OPC according to the decreasing pattern size. Model based correction was first applied to
the optical proximity phenomenon because the image of sub-wavelength pattern is distorted severely during the optical
image transformation. In addition, more tight CD control required to compensate the process induced error effects from
etch or other process as well optical image can be achieved.
In this paper, we propose advanced OPC method to obtain better accuracy on the final target for sub-90nm technology.
This advanced method converts measured CD data into final CD target by using an equation. We compared the results
from the data converting method, suggested in this paper, with those from post-litho(DI), post-etch (FI) OPC model step
by step. Finally we confirmed that advanced new OPC method gives better accuracy than that from conventional OPC
model
Flare has been important variable to achieve good CD control in low k1 lithography. Early works on flare
have focused on long-range DC and local flare, with an attention on how to measure flare and how flare
impact on CD control within theoretical model for ideal situation. As pattern size decreases below 100 nm,
however, short-range flare begins to appear prominently beyond that technology node. It has been pointed
out that process conditions such as photo resist thickness, substrate film stacks, and even some times
photo masks can be important variables for short-range flare but impact of process variables on flare at
illumination level has less been understood yet. Recently, Yun et al. have shown that the illumination
conditions such as coherence factor and illumination aperture shapes also give impact on short-range flare.
They found that the amount of short-range flare, the additional portion of the diffraction image to the
ideal one, increases as the illumination aperture size increases but inner radius of the annular illumination
apertures affect little on the amount of the short-range flare.
In this paper, as the series of the experiments by Yun et al., we will prove detailed relation between
illumination aperture shapes and the short range flare by exploring its impact with number of off-axis
illumination apertures including multi-pole illumination apertures, in addition to the previous data on
partially coherent conventional and simple annular illumination apertures. We utilize the 193-nm scan-and-step exposure tool and evaluate the short-range flare by measuring CD on the 100 nm lines surrounded by clear window having various open ratios. The extended data on various off-axis
illumination apertures reveal clarify the impact of illumination aperture shape on the short-range flare.
Deep-UV (DUV) lithography has been developed to define minimum feature sizes of sub-100 nm dimensions of devices
semiconductor. In response to this trend, DUV mask technology has been proposed as an effective technique for
considering the reduction of mask making cost, especially, in low volume designs. However, the requirement of tight CD
control of the mask features in advanced devices is resulted in increasing of mask cost. In this research, we discussed
two different typed image tones comparison, positive and negative tone, in DUV lithography. The choice of final mask
tone needs to be selected as function of pattern density and shape. The evaluation items to judge if the mask is good are
the OPC model accuracy, resolution and mask throughput. Both mask process and manufacturing throughput are affected
by image tone type of positive and negative. This paper will show the procedures and results of experiment.
In recent years, model based verification for optical proximity effect correction (OPC) has become one of the most
important items in semiconductor industry. Major EDA companies have released various softwares for OPC verification.
They have continuously developed and introduced new methods to achieve more accurate results of OPC verification.
The way to detect only real errors by excluding false errors is the most important thing for accurate and fast verification
process, because more time and human resource are needed to inspect the result of verification as increasing false errors.
A major source of false errors is bending patterns. The number of those from bending patterns is over thousands and they
are inevitable. The most verification tools have the scheme for excluding those by using CD error non-checking or
filtering area. Real errors around bending pattern will not be able to detect with too big size of area, while too many false
error will be reported with too small size of area. Since currently most verification tools had only a fixed area size for
filtering, it has been impossible to achieve most accurate and efficient verification results. Through the optimization of
area size with different corner length, we could get more accurate and efficient results and decrease the time for review
to find real errors. In this paper, the suggestion in order to increase efficiency of OPC verification process by using
different size of CD error non-checking area with various corner lengths is presented.
KEYWORDS: Optical proximity correction, Bridges, Model-based design, Photomasks, Neodymium, Lithography, Data modeling, System on a chip, Logic devices, Process modeling
Conventional OPC fragmentation method operates under a set of simple guiding principles. All patterns are to be
uniform in finite size from edge of polygon. Within each fragment, the intensity profile (aerial image) and edge-placement
error (EPE) are calculated at a settled location. Finally, the length of the entire fragment is moved to correct
for the EPE at that location. This is to be often against simulation like a model based OPC. In the strict sense, model
based OPC is depended on simulation results not only moving of all fragments in the layout are reduced to zero but also
dividing of all polygon edges. This drastically increased data volume and the computation time required to perform OPC.
Therefore, more powerful fragmentation mechanism will be one of major factors for the success of OPC process.
In this study, a new approach of fragmentation has been tested, which reduces OPC correction error. First, we check
the weak point of all patterns using slope, EPE, MEEF and contrast. Second, weak points apply high frequency
fragmentation based on simulation contour images. The others are divided into normal correction recipe. This improves
to accurate OPC correction for weak point which can divide a fine classification. It also is possible to reduce OPC time
for non critical pattern applied moderate fragmentation.
OPC(Optical Proximity Correction) has become an indispensable tool used in deep sub-wavelength lithograph process enabling highly accurate CD (Critical Dimension) control as design rule shrinks. Current model based OPC is a combination of optical and process model to predict lithography process. At this time, the accurate OPC model can be made by accurate empirical measurement data. Therefore empirical measurement data affects OPC model directly. In the case of gate layer, it affects to device performance significantly and CD spec is controlled tightly. Because gate layer is hanging on between active area and sti area, the gate CD is affected by different sub layer stack and step height. This paper will analyze that the effect of sub layer on the OPC model and show difference EPE value results at the patterns such as iso line, iso space,pitch, line end and T_junction between poly and gate model using constant threshold model.
KEYWORDS: Optical proximity correction, Logic, Databases, System on a chip, Data modeling, Photomasks, Instrument modeling, Manufacturing, Electronics, Distortion
It is becoming difficult to achieve stable device functionality and yield due to the continuous reduction of layout dimensions. Lithographers must guarantee pattern fidelity throughout the entire range of nominal process variation and diverse layout.
Even though we use general OPC method using single model and recipe, we usually expect to obtain good OPC results and ensure the process margin between different devices in the sub-100nm technology node.
OPC Model usually predicts the distortion or behavior of layout through the simulation in the range of measured data. If the layout is out of range from the measured data, or CD difference occurred from the topology issue, we can not improve the OPC accuracy with a single OPC model.
In addition, as the design rule has decreased, it is extremely hard to obtain the efficient OPC result only with a single OPC recipe. We can not extract the optimized single OPC recipe which can cover all the various device and layout. Therefore, we can improve the OPC accuracy and reduce the turn around time related to the OPC operation and mask manufacturing in sub-100nm technology node by applying the optimized multi OPC recipes to the device which contains the various patterns like SoC.
KEYWORDS: Photomasks, Semiconducting wafers, Deep ultraviolet, Lithography, Laser systems engineering, Electron beam lithography, Critical dimension metrology, Scanners, Back end of line, Data modeling
The higher productivity of the DUV laser mask lithography system compared to the 50-KeV e-beam system offers the benefit of mask cost down at low k1 lithographic process. But the major disadvantage of the laser mask writing system is rounding effect of contact hole and line end. In this paper, we study wafer process margin effect of corner rounded contact hole and present mask CD specification of corner rounded contact hole written by DUV laser lithography system compared to 50KeV writing tool. The contact hole rounding changes contact hole area at the same mask CD and also change MEEF(Mask Error Enhancement Factor) even though the contact hole area is compensated by adjusting mask bias. If one change EBM3500 mask writer machine to Alta4300 mask writer machine for 160nm contact hole using KrF and 6% HT-PSM, one has to change mask bias, 3.2nm, to meet same wafer process condition.. The MEEF of ALTA4300 mask is 1.6% higher than that of EBM3500 mask at same effective target mask CD. And the mask CD specification written by ALTA4300 has to be set more tightly about 1.3 ~ 1.5% to meet same wafer process margin with EBM3500 mask.
The trim process with organic BARC to fabricate sub-90 nm gate was developed with ArF lithography.
This trim process is not required extra hard mask layer which we usually use to overcome weak etching
resistance of ArF photoresist. BARC etching step has been chosen as the best layer to apply trim
process. We understood that the mix ratio of Cl2/O2 is the key process parameter to control etching bias.
Also we observed that ID bias by changing BARC etching time. PCM and TEM inspection results proved
that excellent transistor performance without any issues. LER improvement was observed by trim process
application. and it helps to improve device performance. This organic BARC based trim process showed
very promising results for sub-90 nm gate patterning.
The advanced lithography needs to be tightly controlled in various areas of lithography. The mask CD specification is one of new areas required much tighter control. Typically, mask CD error can be sorted as two different categories. One is Mean-to-target (MTT) and another is CD uniformity (CDU). The MTT is the difference between the target value and the average value of the measured CD on the mask. CDU means CD uniformity across mask. Those two potential errors can be magnified on the wafer level due to the MEEF. To overcome the MTT, we can adjust expose dose to compensate mask CD error so that we achieve targeted CD on the wafer level. However, the changing expose dose also induces process window change due to the MEEF. It means that we have narrower process window even if we get the targeted CD on the wafer level. On the other hand, CDU can give two different effects on the wafer level. One is narrower process window due to magnified ACLV (Across Chip Line-width Variation) due to the MEEF. Another effect of CDU is the poor OPC accuracy caused by different MEEF as function of pitch. For example, we assume that CD difference of dense line and isolated line is 10 nm on the mask. However, on the wafer, this 10 nm can be magnified as 20 nm by MEEF difference between two structures. Therefore, we think that the mask specification needs to take account those effects. In this paper, we will show technical data to prove how MTT and CDU impact on process window and OPC accuracy. And we will show how we have to make mask specification to overcome those effects.
Flare has been important variable to obtain good CD control in the resolution limited lithography area such as sub-90 nm node. So far, many papers have been reported about how to measure flare and how flare impact on CD control. And some papers have tried to understand theoretical mechanism of flare. However, we expect that the illumination apertures such as the partial coherence factors or the modified illumination aperture shapes would also give impact on the flare. The short-range flare is changing as the open ratio variation on the mask. We assume that the illumination aperture shape change will also give similar effect as the open ratio variation on the mask. In this paper, we will show how the illumination aperture shapes give effect on short-range flare. Experiments were done for 100 nm lines surrounded by clear window having different width from 1 μm to 20 μm. We utilized the 193 nm scan-and-step exposure tool with the partially coherent conventional and off-axis illuminations apertures. In conclusion, we will prove the relationship between flare and illumination apertures.
Optical Proximity Correction (OPC) often reaches its limitation, especially low-k imaging. It results in yield drop by bridging, pinching, and other process window sensitive issues. It happens more when the original layout contains OPC-unfriendly patterns. With OPC-unfriendly layout, OPC model generates totally unexpected results such as narrow space, small jog, small serif and etc. Those unexpected OPC results induce bridged patterns as well as narrow process margin. And they will give direct yield loss of device.
Thus, it is critical to implement the flow for Litho Friendly Design (LFD) and nevertheless simulation-based OPC verification. In this study, a new approach of OPC has been tested, which contains the simulation based analysis of OPC failure and in turn out reconstruct OPC features in a way to fix not only bridging and pinching but also to improve process window. This proves to reduce mask respin by 50% or more. It also has been tried to be a complementary checking in addition to conventional CD monitor in pilot production.
Since an OPC engine makes model to fit wafer printed CD of OPC test mask to simulation CD of test pattern layout, the target CD of OPCed mask is not design CD but the CD of OPC test mask. So, the CD difference between OPC test mask and OPCed mask is one of the most important error source of OPC. We experimentally obtained OPC CD error of several patterns such as iso line, iso space, dense line, line end, effected by the mask MTT (mean to target) difference of the two masks on of 90nm logic pattern with an ArF attenuated mask having designed different MTT. The error is compared to simulated data that is calculated with MEEF (mask error enhancement factor) and EL (exposure latitude) data of these patterns. The good agreement of the experimental and calculated OPC error effected mask MTT error can make OPC error are predicted by mask CD error. Using by these calculation, we made mask CD window to meet OPC spec for 90nm ArF process.
As design rule is decreased, OPC accuracy has become the crucial factor for achieving stable device functionality and yield. Usually the lithography and the etching process conditions are main parameters impacting to the OPC accuracy. The OPC accuracy can be changed as function of process conditions, even if we use same OPC model. And we usually expect to obtain same OPC results between different devices in same technology node if we used same OPC model and process. But we observed different OPC results as function of devices as well as process conditions. We suspected this phenomenon was resulted from the different pattern density induced global etch bias variation. First of all, we will prove that the device dependency of OPC accuracy is come from pattern density induced etch bias effect. Finally, we will setup new OPC methodology to compensate this effect.
Recently, the scatterometry is becoming more and more popular as a inline metrology tool for lithography process control as well as etching process control because of the advantage of fast measurement with high accuracy. Especially, at the gate patterning that fabricates transistors, the scatterometry can be very powerful because it gives massive volume of CD (Critical Dimension) measurement data and gate poly profile, simultaneously. Those results could help to understand and forecast the performance of transistors. In order to achieve accurate and consistent measurement results by scatterometry, the setup of stable model and library is very crucial since it has nature of indirect measurement. For example, as defining of substrate conditions, modeling range of parameters, target values and type of models, scatterometry (in this paper, we call as OCD; Optical CD) gives different results even if we use same data basis. In this paper we have shown the best practice how to optimize variables of scatterometry to get accurate and stable results. We used the OCD(Optic CD: Accent CDS200) angular scatterometry system which can rotate HeNe laser light source from -47 to +47 degree. In order to investigate the substrate dependency, various silicon wafer substrates having periodic patterned with different materials such as photoresist, BARC, poly silicon, and thermal oxide film has been used. Finally, we observed OCD has the excellent capability for inline process controllability.
Photolithography is the driving technology and key enabler for the fabrication of integrated circuits with continuously decreasing feature sizes. Currently, state-of-the-art photolithography materials and processes can fabricate sub-100nm features, but significant technical hurdles remain in making sub-100nm features. These challenges include the understanding of LER (Line Edge Roughness) that will have a broad industrial impact. The 193nm resist has a thin gel layer at the interface of the developed resist and the developer, and resist patterns are formed by random detachment of this gel layer during development in the developer. Since the detachment of gel layer occurs randomly within the gel zone, LER increases in the case of higher gel layer thickness. This gel layer thickness can be determined by gel layer development model which consider two simultaneous reactions at the front and back of gel layer during dissolution of gel layer in the developer. This study attempts to explain LER using the concept of gel layer of which thickness is determined by hydrophilic and hydrophobic balance depending on the formulations of chemically amplified photoresists. LER can be minimized if we control the hydrophilic and hydrophobic balance by tuning the structure of polymer backbone in chemically amplified photoresists and minimize the gel layer thickness.
This paper presents a methodology for modeling the space printability at the gate level in 193nm lithography. Spaces are shown to be more susceptible to process variations and lens aberrations than lines are. Experimental Scanning Electron Microscopy (SEM) pictures show that the scum and bridging effects can occur in spaces although all the line critical dimensions (CDs) are on target. A resist imaging model is used to simulate the line CDs through defocus, pitch and size, and the prediction error is within 5nm. However, this model can not reasonably predict space CDs without using variable threshold, which is explained a proposed trajectory dissolution rate model. Based on the dissolution model, a process rule checker is proposed which inspects the peak light intensity in a space and compares it with a given threshold. This condition is verified experimentally.
The feasibility study to use high NA ArF lithography for 70 nm process development was done. After intensive simulation works, new forbidden-itch behavior of alternating PSM in low k1 imaging was found out. This forbidden pitch due to extremely small MEF and OPE of alternating PSM at small (sigma) . In order understand the mechanism and behavior of the forbidden-pitch, simulation and experiment were done as function of critical parameters of NA, (sigma) and wavelength. Solution to control forbidden-pitch for low k1 imaging of 70 nm has been address as critical item which needs to be overcome.
ArF lithography is pushing its limit to beyond the 100-nm node due to delay of NGL technologies to meet the aggressive insertion schedules. However, lithography process for 100-nm node with binary mask and ArF resist is still not easy to achieve and will be one of the big challenges for lithography community. Although there have been significant improvements over the past year, ArF resists remain as the most critical aspect in ArF lithography development. Areas of concern for ArF resist include; higher level of environmental instability compared to KrF materials, different response depending on the tone of reticles, and different performance exhibited between microsteppers used for initial development and full field scanners to be used in manufacturing. We expect that these problems will be getting worse in sub 100-nm node. To achieve the most challenging performance goals, the resist to be used in manufacturing will require optimization of the chemical formulation of commercialized resists based on specific design requirements, process and environmental conditions. This paper will describe an extensive DOE (design of experiments) that was performed in order to find better resist formulation from commercialized resists for our specific FAB environment. PAG, resin and amine were main three components for this DOE. After choosing the best resist for 100-nm node, we have will evaluated actual lithographic performance capability such as DOF, exposure latitude, etc.
Selective strong phase shift mask techniques, whereby a phase-shift mask exposure is followed by a binary mask exposure to define a single pattern, present unique capabilities and problems. First, there is the proper exposure balance and alignment of the two masks. Second, there is the challenge of performing optical proximity correction that will account for two overlaying exposure models and masks. This is further complicated by the need to perform multiple biasing and adjustments that are often required for development processes. In this paper, we present results for applying a new OPC correction technique to a dual exposure binary and phase-shift mask that have been used for development of 100 nm CMOS processes. The correction recipe encompasses two models that were anchored to optimized processes (exposure, NA, and ?). The correction to the masks also utilized boolean techniques to perform selective biasing without destroying the original hierarchical structure. CMOS technology utilizes isolation with pitches of active device regions below 0.4 ?m. The effective gate length on silicon is in the range of 0.08 to 0.18 ?m. Patterning of trench openings and gate regions are accomplished using deep-UV lithography.
Two lithography strategies - of alternating PSM using double expose method (DEM) and high transmission attenuated PSM - were investigated to assess their capability for printing 0.1 micrometers gate. In order to do that, the optimization of each process has been carried out for maximizing the process window; of depth of focus (DOF) and expose latitude (EL), to make them satisfy process requirement generated by focus and expose budget study. The key components of optimization are finding the best NA and sigma, the optimum bias for isolated lines and dense lines and the optimum transmission of att PSM. Then, the impacts of some critical lithographic parameters such as phase error effects in APSM, proximity effects and mask error factor (MEF) were determined with experimental data. As final answer to the question of process capability of two lithography techniques for 0.1 micrometers gate patterning, CD control analysis was made to see if they satisfy our gate CD control requirements.
The aggressive schedule for downscaling of gate dimensions and need for tight CD control for the 130nm node has created the need to seriously consider the use of a Levenson phase shift mask with 248nm lithography tools. The improvements in exposure latitude and depth of focus of strong phase shift over binary patterning are well known and have been clearly demonstrated. What is less well understood is the impact of the mask error factor.
The timing of 193nm tools and the resist to support them is driving semiconductor manufacturers to plan for production of sub-half lambda features on 248nm exposure tools. Lithographers are turning to reticle enhancements to close the capability gap, finding that there are a myriad of issues that must be addressed to achieve production- worthiness.
Optical lithography, since many years the workhorse in manufacturing of integrated circuits, is being pushed to its limits. The extension of photolithography has been made possible by improvements in resist schemes and by resolution enhancement techniques. Although the resolution capabilities are available, maintaining CD-control will be one of the major challenges for photolithography engineers in the future. Traditionally, focus and exposure latitude are the principal criteria used in lithography. In this paper, we use an alternative method to quantify the performance of a lithographic process, based on an in-house developed software package Norman-Debora. By first modeling the CD-dependency on various input variables (focus, dose, resist thickness, reticle CD,...), Norman predicts the CD-distribution based on assumed variation intervals for these input variables. The goal of this paper is to compare the predicted CD spread by Norman with the experimentally measured CD distributions focused on the poly layer of a quarter micron CMOS process.
When small feature delineation is considered using existing exposure tools, special techniques might be needed such as phase shift mask, oblique illumination, top surface imaging, etc. When different types of patterns exist simultaneously or island patterns exist predominantly, optical proximity effect will become more important to be controlled. In this study, six different mask types were prepared and evaluated in view of a pattern fidelity and process latitude for 256 mega bit DRAM's storage node patterns. The masks used for this experiment were conventional transmission mask, serif patterned mask, square patterned Transmittance Controlled Mask (TCM), horizontally rectangular TCM, vertically rectangular TCM, and cross patterned TCM. The cross patterned TCM had three different transmittance on it and was evaluated also. In view of both pattern fidelity and process latitude, cross-TCM showed the best result. The vert-TCM also showed fairly good result. But the worst results always came from the conventional mask. From plane surface area point of view, once serif mask or TCMs are used, the areas always improved ranging from 120% to 145% at the best focus condition compared to the convention mask. There was not so much difference among three different transmittance in view of pattern fidelity and process latitude. As one of candidates for optical proximity correction, since small serif delineation on mask level is not easy for devices with small features such as 1 giga bit DRAM or beyond, TCM is more promising which has much bigger and easily writable gray area.
The off-axis illumination technique either using a quadrupole aperture or diffracting grating was known as a good method to enhance both resolution and depth of focus. Severe variations of critical dimension over topography area were observed in our initial experiments using advanced tilted illumination on mask (ATOM) on our actual device. In this paper, the difference of standing wave effect between ATOM and conventional illumination is analyzed and compared in view of two different resist systems, bleachable and non-bleachable resists, and the polarization affect of the stepper. As a result, bleachable resists show worse standing wave effect in ATOM than in conventional illumination. Non-bleaching resists, however, show no difference in standing wave effect for both ATOM and conventional illumination. This is in good agreement with simulation results. In conclusion, because standing wave effect is not only a function of resist thickness but also a function of bleaching rate, Dill's parameters A, B, and C should be controlled as well as resist thickness especially for off axis illumination.
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