EUV lithography is expected to begin production in 2014. Production of successful EUV photomasks requires patterned
mask inspection (PMI). The ultimate PMI tool is expected to utilize actinic (EUV) illumination. Development of such a
tool is expected to require three years after funding. Current test EUV masks, such as 22 nm, can be inspected using 193
nm wavelength deep UV (DUV) inspection tools similar to those currently being used for DUV masks. The DUV
inspection tools may be extended for the 16 nm node. However EUV production is expected to start with 11 nm node
masks which cannot be inspected with proposed DUV inspection tools. Therefore E-beam inspection (EBI) is discussed
as the interim PMI method.
EBI has the advantage of high resolution and the disadvantages of low inspection speed and relative insensitivity to ML
defects (in the multi-layer material). EBI inspection speed is limited by the pixel size, pixel capture rate and the number
of electron columns. The pixel rate is limited by the detector time-resolution, the beam current, and the detection
efficiency.
Technical improvements in beam focus, secondary electron detection, and defect detection and analysis provide good
performance for 22 nm node masks. We discuss the advances and show that performance can be extrapolated for 16 and
11 nm node patterned mask inspections.
We present sensitivity and false-defect frequency results of using the Holon EBI tool on 22 nm test masks and a roadmap
for extending its operation for use on 16 and 11 nm node masks for inspections requiring 2-5 hours per mask.
Mask defect disposition gets more difficult and time-consuming with each progressive lithography node. Mask
inspection tools commonly use 250 nm wavelength, giving resolution of 180 nm, so critical defect sizes are far less than
the optical resolution - too small for defect analysis. Thus the rate of false or nuisance defect detection is increasing
rapidly and analysis of detected defects is increasingly difficult. As to judging the wafer printability of defects, AIMS
(Aerial Image Measurement System) tools are commonly used but are also time-consuming if defect count is high. For
improving the efficiency of mask defect disposition, we propose the combination of a SEM defect review tool and defect
disposition and simulation software, which use high-resolution SEM images of defects to do defect review, defect
disposition, and wafer printing simulation of defects automatically or manually.
The SEM defect review tool, DIS-05 developed by Holon Co. Ltd., is designed for defect review and disposition using
reference images derived from e-beam files or CAD database. This tool uses the Automated Defect Analysis Software
(ADAS) developed from AVI LLC. to interface the inspection tool and the DIS-05. ADAS detects false defects before
SEM imaging and performs aerial image simulation from the SEM and CAD images to estimate the wafer CD error
caused by each defect. We report on its speed (>300 defects/hour), classification accuracy and simulation accuracy when
used with masks at the 45 nm technology node and beyond. This combination of SEM and ADAS is expected to
significantly accelerate process development and production for the 45 and 32 nm nodes. It will also increase the masksper-
day throughput of inspection and AIMS tools by shifting most defect review to ADAS software using SEM images.
At preliminary tests showed the combination tool can do auto defect disposition and simulation with promising results.
KEYWORDS: Capacitance, Resistance, Signal processing, Signal analyzers, Semiconductors, Inspection, Signal detection, Manufacturing, Sensors, Measurement devices
We analyzed substrate current signal of flash memory with floating and control gates using EB-Scope for the
measurement of bottom CD. We showed that the signals come from capacitance structure of the floating and control
gates. From this analysis, we showed we can get the information of electrical characteristics of floating and control
gates such as capacitance, resistance and time constant as well as the bottom CD of flash memory with floating and
control gates. This technique form this analysis can contribute yield enhancement in flash memory manufacturing
process by in-situ monitoring.
We compare substrate current (SC) values for thin SiO2 films, with thicknesses ranging from 2 nm to 200 nm, between modeled simulation results and actual measurements made by EB-SCOPE, a substrate current measuring instrument. The simulation models use Monte Carlo methods to model the generation of secondary electrons (SE) and holes, and use 1-D charge transfer to simultaneously model SE yield and SC values to quantify thin film thickness in order to predict if a high aspect ratio contact or via hole is closed or open. The simulation results show a strong match with the measurement data. The SC value can be used for assessing process uniformity as well as detecting process related failures, in this case a closed contact hole which can be seen in the qualitative SC images. We can also apply this modeling to monitoring of surface preparation and clean processes to detect residual films such as SiO2. The method can detect changes in surface state conditions, such as residue or oxide formation, as changes in SC values.
This paper presents the concept of "copy result exactly" frameworks using EB-SCOPE technology which must be a powerful tool for coping the best process condition producing ever lasting good contact and via hole.
KEYWORDS: Semiconducting wafers, Process control, Silicon, Silica, Electron beams, Yield improvement, Etching, Scanning electron microscopy, Semiconductors, Control systems
This paper presents the concept of 'copy result exactly' frameworks using EB-SCOPE technology which must be a powerful tool for coping the best process condition producing ever lasting good contact and via hole.
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