Intensity Modulation and Direct Detection (IMDD) technology, with its low latency, low power consumption, and high throughput advantages, has emerged as the preferred solution for high-efficiency data transmission and exchange between large-scale computing clusters. Digital Signal Processing (DSP) technology can further enhance IMDD transmission performance by compensating for transmission impairments. In this paper, we propose a Functional Link-based Volterra equalizer (FL-Vol) that combines the Functional Link Artificial Neural Network (FLANN) and the Volterra equalizer (Vol). The FL-Vol demonstrates superior nonlinear characterization capabilities, benefiting from higher-order terms in the extended basis functions and cross terms in the Vol. We select the classical Least Mean Square (LMS) criterion for self-adaptive parameter iteration and utilize a variable step-size algorithm based on a modified sigmoid function to balance the rate of convergence and steadystate error. We validate the equalization performance of FL-Vol through a single lane 112Gbps O-band PAM-4 IMDD transmission experiment. Our performance comparison of these equalizers reveals that the 2nd-FL-Vol offers up to a 2dBm improvement in equalization performance with similar computational complexity compared to the 2nd-Vol. Furthermore, the 2nd-FL-Vol reduces computational complexity by approximately 30% while maintaining similar equalization performance compared to the 3rd-Vol. Notably, despite the theoretical advantage of the 3rd-Vol structure in nonlinear characterization, the 2nd-FL-Vol consistently outperforms the 3rd-Vol, especially at higher received optical powers. Additionally, as expected, the variable step-size algorithm improves the performance of all equalizers.
An efficient and tolerant chip-to-chip optical coupling approach employing silicon nitride grating couplers was proposed and investigated. The integration of bottom mirrors and the strategic extension of grating length led to notable results, with a peak coupling loss of -0.28 dB and a 1-dB alignment tolerance along the x-axis reaching 25.4 μm when using a grating length of 50 μm.
The edge coupler holds paramount importance as a link bridging optical signals between fibers and silicon-based optoelectronic chips. It surpasses the grating coupler in terms of elevated coupling efficiency, diminished polarization sensitivity, and an expanded bandwidth. However, designing a low-loss silicon edge coupler with a broader minimum width, especially for the O-band, presents substantial obstacles. To surmount these challenges, a silicon nitride (SiN)- assisted double-etching silicon structure with a 180 nm minimum width is adopted in this work. This innovation capitalizes on the double-etching silicon taper, propelling the SiN layer's height to 1.6 μm relative to the bottom of silicon waveguide, resulting in pronounced reduction of silicon leakage loss. By meticulously implementing coupled mode theory, an exceptional coupling efficiency exceeding 0.95 is achieved for both TE and TM polarizations at 1310 nm, facilitating the seamless transition of light from SiN to the thinner silicon waveguide. Further enhancements in curbing silicon leakage loss and shortening device length are achieved through mode analysis-driven designs for both the SiN and silicon taper. Ultimately, these intricate designs culminate in an edge coupler boasting a 180 nm minimum width, with minimal losses of approximately 0.7/1.5 dB for TE/TM polarization and a 0.5-dB bandwidth of around 100 nm within the O band, as demonstrated through simulation while interfacing with standard single-mode fibers.
We demonstrate a high-efficiency silicon nitride grating coupler for perfectly vertical coupling. The directionality of the diffraction process is improved with the help of the bottom mirror and Bragg reflectors introduced in the design, leading to the minimal coupling loss of -0.52 dB at 1315.6 nm.
O-band edge couplers exhibit significant promise in silicon-based optoelectronic chips, particularly for applications within data centers. However, the task of designing a low-loss O-band silicon edge coupler with a wider minimum width, capable of interfacing with standard single mode fibers (SMF), presents greater challenges compared to its C-band counterpart. In this work, we propose, design and simulate a three-etching silicon edge coupler devoid of a cantilever structure, leveraging a 130 nm CMOS process. By incorporating a silicon oxide cladding with a refractive index 0.007 greater than that of the buried oxide, we successfully mitigate silicon leakage losses, particularly for the TM mode. Furthermore, we introduce a novel taper shape design methodology rooted in mode analysis. Within this designed taper shape, the effective refractive index or area of the supported mode experiences an equal rate of change as the taper width increases. Thanks to these innovative designs, our simulations reveal a minimum loss of 0.82/1.68 dB and a loss range of 0.69/0.38 dB for TE/TM modes in the O band when interfacing with standard SMF. Most notably, our edge coupler, featuring the designed taper shape, demonstrates an average coupling loss improvement of 1.23/0.44 dB for TE/TM modes compared to the parabolic counterpart. This work introduces a novel taper shape design approach for compact and low-loss edge couplers, offering a practical solution for achieving low-loss SMF-chip coupling within the O band.
Silicon nitride photonic integrated circuits with ultra-low loss are widely used in applications such as telecommunications and optical sensing. However, the radiation loss increases rapidly as the radius is reduced, resulting in large-sized silicon nitride photonic integrated circuits. The weak thermo-optical effect limits the high-efficiency, low-power consumption applications. In this paper, a stepped index waveguide structure is studied to reduce the bending loss by enhancing the mode confinement. A bend with a radius of 30μm is designed using Ansys MODE. Polymer with a high thermo-optic coefficient is used as the cladding of the silicon nitride waveguide to improve the tuning performance of the phase shifter. The grooves around the waveguide also acts as an adiabatic trench to increase the efficiency of the thermal electrode. A π phase shift under thermal tuned power of 7.5mW is achieved with a 300μm long silicon nitride waveguide. Finally, a cascaded silicon nitride micro-ring resonator with radius of 50μm is designed to achieve an efficient filter with a wide tuning range of 116nm. This scheme provides a novel approach for high-density, wide-tunable and miniaturized devices in silicon nitride photonic integrated circuits.
Bilayer molybdenum ditelluride (MoTe2) exhibits promising research potential in silicon-based optoelectronics due to its near-infrared emission band. Although previous studies have shown that the direct and indirect bandgaps are closely located, the origin of the dominant exciton in photoluminescence (PL) emission and the energy difference between the direct and indirect bandgaps remain uncertain. To address these issues, we performed comprehensive micro-PL and absorption measurements on monolayer and bilayer samples, incorporating electrical control, across a wide temperature range of 4 to 300 K. These systematic measurements determined that the dominant PL emission in bilayer MoTe2 arises from an intralayer exciton with a direct bandgap and the energy difference between the direct and indirect bandgaps in the bubble-strained bilayer sample with a strain of approximately 1% was estimated to be around 10 meV in experiment, consistent with theoretical calculations in the literature.
The implementation of IM-DD optical communication systems requires low cost, power consumption and latency, making low complexity and high real-time deployment potential digital signal processing (DSP) a critical component. The clock synchronization algorithm plays a crucial role in ensuring real-time deployment by eliminating sampling clock deviation at the transceiver and optimizing the signal sampling position. In this context, we proposed an enhanced clock synchronization scheme based on the classic Gardner algorithm, which effectively addresses the widespread timing jitter issue in the synchronization loop while maintaining computational efficiency. Through comparative experiments of multiple single-lane 112Gb/s PAM-4 IM-DD transmissions, we demonstrated that our clock synchronization scheme is capable of effectively compensating for the clock offset in a high-speed 100Gb/s+ IM-DD transmission system. Our experimental results show that the algorithm achieves a correction accuracy of 1 part per million level, which is comparable to the receiver sampling frequency in the transmission (GHz). Moreover, the importance of clock synchronization for IM-DD systems is also highlighted by comparing signal quality with and without the algorithm. Without an equalizer to compensate for signal degradation after using a clock synchronization algorithm, the constellation can still be obtained clearly. If not perform the clock synchronization, a clear constellation cannot be obtained even with an equalizer. This is manifested in the signal-to-noise ratio, which our clock synchronization algorithm can bring the improvement of more than 1 dB. Additionally, the bit-error-ratio can be improved by about 5 numerical levels under specific modulation amplitude.
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