High speed data links with low jitter and large bandwidth are essential for millimeter-wave (mmWave) communications. In this paper, an analog-domain 4-level pulse amplitude modulation (PAM4) baseband demodulation circuit with low data jitter and ultrahigh data rate was designed. In order to suppress the jitter caused by inter-symbol interference (ISI), a local feedback loop was introduced to extend the bandwidth of threshold slicer. A novel clock and data recovery (CDR) circuit architecture was proposed and optimized to extract the clock pulses with low jitter, thus improving the recovered data quality. A symmetric decoder performs an XOR logic operation to recover the least significant bit (LSB) of PAM4 signal, while the most significant bit (MSB) can be directly obtained from the middle-lane after retiming. The whole demodulation circuit was optimized based on IHP 130nm SiGe BiCMOS technology, and the simulation results indicate that our designed circuit can decode single-channel 50 Gbit/s PAM4 data streams into two 25 Gbit/s NRZ signals, and the peak-to-peak jitter is less than 0.1 UI.
Although millimeter wave (mmWave) wireless communication has the advantages of huge bandwidth, narrow beam and high transmission quality, it also suffers from severe signal attenuation caused by atmospheric absorption and short distance transmission. Therefore, the equalization techniques are normally required in mmWave links. In this paper, a continuous time linear equalization (CTLE) with variable gain for mmWave receiver was designed in IHP 130 nm SiGe BiCMOS process. The CTLE circuit incorporates an active equalizer with negative capacitance converter and a variable gain amplifier (VGA). The negative capacitance structure was used to increase the peaking gain at Nyquist frequency to compensate for the high frequency loss, and the VGA provides an adjustable low frequency gain. The simulation results demonstrate that the tuning capabilities of 12 dB and 5 dB can be respectively achieved for low frequency and high frequency, and the equalization performance is verified for two different channels at 25 Gb/s NRZ data streams.
Millimeter-wave (mmWave) technology has been employed in many applications due to abundant bandwidth resources and high interference immunity such as telecommunication, automotive radars, and imaging. In this paper, a mmWave transmitter link incorporating PAM4 modulation, resonant tunneling diode (RTD) based oscillator, power amplifier and antenna was proposed. To achieve good linearity and alleviate inter-symbol interference (ISI) caused by channel loss simultaneously, a PAM4 modulation circuit utilizing voltage mode driver and 2-tap pre-emphasis was designed and optimized in TSMC 28 nm CMOS process. The simulation results show that our PAM4 modulation circuit operates properly at 40Gb/s with a differential output swing of up to 800 mVpp under a supply voltage of 0.9 V. The overall power consumption is about 51.3 mW, corresponding to an energy efficiency of 1.28 pJ/bit.
We demonstrate optical bistability in InP/InAlGaAs multi-quantum well(MQW) semiconductor ring lasers(SRL) which
are fabricated by the use of inductively coupled plasma reactive ion etching (ICP-RIE) and can be used in a multi-ring to
achieve all-optical storage. Unlike other international reports, the observed optical bistability has unidirectional regime
started directly from the threshold, skip the first two regimes and greatly reduce the injection current required in
applications. The device described in this article achieves threshold current 56mA which is quite low compared to other
reported devices, and some analysis and experiments on the etching depth have been done.
Silicon-based optical interconnection can solve the problem in interconnection of ULSI, can be used in optical
communication and can be used in optical calculation in future.
A complete Silicon base interconnection optoelectronic system is achieved, which is composed of light emitting
diode (LED), driver, detector, and amplifier. Main attention is to prove the feasibility to fulfill optical
transmission and detection in using Silicon material, and obtains enhancement of optoelectronic conversion
efficiency at the same time.
The phenomenon of electro-luminescence of Silicon positive intrinsic negative (pin) structure diode is
investigated. The optical spectral response of the system at 700nm indicates that the emitting light source has
low optical loss in Silicon. So the LED is suitable for Silicon optoelectronic interconnection system. The
detector is constructed with the same pin structure, the responsivity spectrum of the detector has a lot of
overlapping area with the spectrum of the LED. So, high transmission efficiency can be achieved in such a
system. Moreover, the driver and the amplifier circuit are all realized with Silicon material.
The performance of that system was tested in ordinary condition. The EL response time achieves to 100ns and
EL quantum efficiency achieves to 0.05%, which is a high level in Silicon optical interconnection.
This system is completely compatible with silicon on isolator (SOI) technique and can serve as a foundamental
basis of the research in the field of optical connection. Possible improvements for the optical connection system
have been discussed.
In this paper, the design and fabrication for a high speed, low crosstalk 12 channels monolithic integrated CMOS optoelectronic integrated circuit (OEIC) receiver module is reported. The module consists of a Si-based photodetector array and front-end circuit integrated receiving chip; printed circuit board (PCB); fiber array; package and shield components. The structure of Si-based double photodiode (DPD) can speed up the receiver but at the same time make the deterioration of responsivity. The adoption of active inductors in TIA circuit can extend the -3dB bandwidth to a higher level. In particular, the design method of low crosstalk is discussed in detail. Instead of conventional isolation methods used to reduce inter-channel crosstalk, we find a novel way to cancel it by study crosstalk issues from a circuit design perspective. The chip fabricated by CSMC (a foundry in WuXi, China) 0.6μm standard CMOS process without any modification to the process or additional post-process steps. This extremely reduced chip fabrication costs. The module has the merit of high speed, low crosstalk and low cost spontaneously. The measured results show that every single channel of the receiver is able to work at bit rates about 1Gb/s. In total the monolithic integrated 12-channel OEIC receiver module can be operated at 12 Gb/s. The module can be used in ultra high speed optical interconnection system.
As the length scale of the devices decreases, electrons will spend increasingly more of their time in
the connections between components; this interconnectivity problem could restrict further increases in
computer chip processing power and speed. Considerable effort is therefore being expended on the
development of efficient silicon light-emitting devices compatible with silicon based integrated circuit
technology.
Here, we describe the electrical and optical properties of Silicon positive intrinsic negative (pin)
structure diode that operates at room temperature. The voltage-current and electroluminescence (EL)
property are measured at room temperature for a silicon pin diode under forward biased current. The
optical spectral response of the system at 700nm indicates that the emitting light source has low optical
loss in Silicon. So the LED is suitable for Silicon optoelectronic interconnection system.[1][2]
The rate-equation model for free carriers on light-emitting pin structure and the equivalent circuit
model based on it have been presented. We have developed a way to calculate the model parameters by
comparison with experimental results. This parameter extraction way can be fully accomplished
automatically by using MATHCAD program and the equivalent circuit model is simulated by using
HSPICE program respectively. The results of both experiment and simulation results are good agreement with each other.
Bipolar/MOSFET hybrid mode lateral transistor is a transistor in which both bipolar and MOSFET currents flow simultaneously. Because of (1) Good compatibility with CMOS technology; (2) Larger current driving capability and transconductance than MOSFET. So, it is suitable to be taken as a bipolar device in BiCMOS element. In this paper, the Si/SiGe heterostructure, under the gate, is introduced into the conventional bipolar/MOSFET hybrid mode transistor. So a hybrid mode transistor with a lateral n+-Si/p-SiGe/n+-Si structure parallel in base is formed, in which the heterostructure of E-B junction n+-Si/p-SiGe has a high injection electron current from E to B region and a low injection hole current from B to E region (result in by higher barrier for hole), then the total injection efficiency will increase. When this effect becomes a main mechanism than that of the barrier lowering in the surface depletion layer, the characteristics of the device will be dependent on the parameters of SiGe alloy, such as the mole number of Germanium etc. The device simulation of Si/SiGe heterojunction base hybrid mode transistor has been carried out by MEDICI program. The simulation results show that IC and hFE increase with Mole number of Ge increasing and WB decreasing, then the current gain and current capability are improved than that of conventional bipolar/MOSFET hybrid Mode transistor.
In this paper, the photo-detected and controlled functions based on silicon photo-electronic Lambda transistor (PLBT) are reported. PLBT is composed of a npn vertical bipolar transistor as main device and a enhancement-mode MOSFET transistor as feedback device which connected in parallel across the base and collector terminals of bipolar transistor. Photo-electronic-lambda bipolar transistor (PLBT) is one important member of Si-photo electronic negative resistance devices. It has wide applications in photo-electronic coupler, light detector, light sensor and other photo-electronic circuit modules, which is significant for the further study of photo-electronic devices and circuits. When the Si-photo-electronic negative transistor device works as a load, it has two stable output states (bistability characteristics) with the change of the input light signals. Using the photo-bistable and self-locking characteristics of the PLBT, a photo-controlled Bistable Logic Circuit Element has been set up successfully. Through detail studying and analyzing to the operation feature and load feature of the photo-controlled bistable circuit, the nonlinear characteristic of the circuit is demonstrated. Furthermore the applications of this circuit element have been studied and verified.
Photo-generated carriers' transmission delay of a CMOS-Process-Compatible double photo-diode (DPD) is analyzed by using device simulation in this paper. The carriers' transmission delay of a DPD in CMOS N-well process consists of three parts: the delay in the P+ region, in the depletion region and in the N-well. The DPD equivalent circuit model, including photo-generated carriers' transmission delay, is given by means of device simulation. By comparing with different depth of the N-well and different area of the DPD, the delay of the diffusion part in the N-well and the delay of the junction capacitance are the most significant factors to determine the delay time of a DPD. In addition, the diffusion delay is relative to the depth, the doping concentration of the N-well and the bias. Adopting smaller size CMOS process is of benefit to improving the speed due to the shallow well, nevertheless the shallow well can cause the responsivity reduce. The responsivity reduce can be compensated by increasing the junction area.
On replacing the npn bipolar transistor by a npn phototransistor in the Lambda Bipolar transistor (LBT), we can get a novel optoelectronic negative resistance detector -- photo-Lambda bipolar transistor (PLBT). In this paper, the photo-negative resistance characteristic of this device has been demonstrated by PSPICE simulation and by a fabricated experimental device. It is shown that PLBT is not only a conventional optical detector but also a basic element in the photo-induced oscillators and in the photo-controlled frequency modulator. A wide variety of application for PLBT can be expected. PLBT is composed of a npn phototransistor as main device and a n-channel enhancement-mode MOSFET as a feed back device which connected in parallel across the base and collector terminals of phototransistor. As the VCE of photo-transistor (as same as VGS of MOSFET) is in excess of threshold voltage VT of MOSFET, then the MOSFET turns on and its drain current Id will shunt the photo-base current Iphb and the collector photocurrent Iph will decrease. The photo-negative resistance characteristic of PLBT will arise. The expressions of Iph and negative resistance RN have been derived from the physical model of PLBT. The simulation results of PSPICE are in agreement with measured data of the experimental PLBT device.
By encapsulating a light emitting diode (LED) with a Silicon photo-negative resistance Device face to face in a hermetic package, a new type opto-isolator has been developed. Because of the features of Bistability and self-latching on the silicon photo-negative resistance devices, these non-linear opto-isolators present the response persistence function for the input signal. In this paper, the demonstration of response persistance function on PDUBAT type of silicon photo-negative resistance device has been made experimentally. The Dual Base Transistor (DUBAT) is a three terminals Voltage controlled negative resistance device, it is composed from the combination of a pnp type lateral bipolar transistor and a npn type vertical bipolar transistor. As DUBAT is radiated by light, the npn bipolar transistor is taken as a phototransistor. Thus the DUBAT will become a photo-DUBAT or PDUBAT. In PDUBAT, it is found that the photo-controlled "S" negative resistance characteristic can introduce a photo-controlled current switching effect and the persistance response functions, which keeps the response state for the input light signal until the reset signal changes the circuit from maintaining state to waiting state.
By using mixed-mode simulator in ATLAS, a commercial simulator produced by Silvaco International, a CMOS-process-compatible opto-electronic integrated circuit (OEIC) receiver is designed. The OEIC receiver can be used in optical communications or optical interconnections. The optical wavelength response, optical frequency response and optical pulse response of the OEIC receiver are simulated in 0.35 μm and 0.6 μm CMOS process. The sensitivity and the bandwidth of the OEIC receiver are optimized in giving detector area. Available receiver bandwidth is optimized under the given input optical power and detector area. The feedback voltage in trans-impedance amplifier is designed both for bandwidth and for sensitivity. The OEIC receiver was fabricated with a 0.6 μm CMOS process through MPW (multi-projector wafer) in China.
We report some investigations on vertical cavity surface emitting laser (VCSEL) arrays and VCSEL based optoelectronic smart photonic multiple chip modules (MCM), consisting of 1x16 vertical cavity surface emitting laser array and 16- channel lasers driver 0.35 )mum CMOS circuit. The hybrid integrated multiple chip modules based on VCSEL operate at more than 2GHz in-3dB frequency bandwidth.
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