In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To
achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled
film edge position and good uniformity around the wafer circumference is needed.
We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The
performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse
system has a good controllability of film edge position and good uniformity around the wafer circumference. The results
indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and
substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to
provide a suitable film stacking architecture for immersion lithography mass production process.
The introduction of Immersion lithography, combined with the desire to maximize the number of potential
yielding devices per wafer, has brought wafer edge engineering to the forefront for advanced
semiconductor manufactures. Bevel cleanliness, the position accuracy of the lithography films, and quality
of the EBR cut has become more critical.
In this paper, the effectiveness of wafer track based solutions to enable state-of-art bevel schemes is
explored. This includes an integrated bevel cleaner and new bevel rinse nozzles. The bevel rinse nozzles
are used in the coating process to ensure a precise, clean film edge on or near the bevel. The bevel cleaner
is used immediately before the wafer is loaded into the scanner after the coating process. The bevel cleaner
shows promise in driving down defectivity levels, specifically printing particles, while not damaging films
on the bevel.
In immersion lithography process, film stacking architecture will be necessary due to film peeling. However, the
architecture will restrict lithographic area within a wafer due to top side EBR accuracy
In this paper, we report an effective film stacking architecture that also allows maximum lithographic area. This study
used a new bevel rinse system on RF3 for all materials to make suitable film stacking on the top side bevel. This
evaluation showed that the new bevel rinse system allows the maximum lithographic area and a clean wafer edge.
Patterning defects were improved with suitable film stacking.
With the introduction of immersion lithography into IC manufacturing for the 45nm node, pattern collapse and line
width roughness (LWR) remain critical challenges that can be addressed by implementing formulated surface
conditioners. Surface conditioners are capable of solving multiple issues simultaneously and are easily integrated into
the post-develop photolithography process.
In this paper, we assessed the impact and reported our findings using a formulated surface conditioning solution in an
immersion lithography process to improve the non-pattern collapse and LWR process windows on 300mm Si wafers
having 50 nm L/S features. The non-pattern collapse and LWR process window results were then compared to wafers
processed using traditional developer processing methods, a DI Water (DIW) rinse.
We report our findings using Focus Exposure Matrix (FEM) wafers having 50nm dense lines/spaces (L/S) and a 2.4:1
aspect ratio to determine the non-collapse and LWR process windows. An ASML TWINSCAN XT:1700TM Scanner
and a 6%attPSM mask were used to pattern the FEM and LWR wafers. The wafers were then developed using an
optimized developer recipe on an RF3iTM coater-developer track. Each wafer was analyzed and evaluated to determine
the impact to CD and LWR with respect to the non-pattern collapse process window
Formulated surface conditioners having dual capabilities, reduced pattern collapse and LWR, have demonstrated that
multiple ITRS Roadmap goals can be achieved and easily implemented into standard IC processing in order to meet
these challenges.
Recently, pattern collapse is becoming one of the critical issues in semiconductor manufacturing and many works have been done to solve this issue1) 2). Since pattern collapse occurs when outer force onto the resist pattern such as surface tension, impact of rinse solution, etc. surpasses the resistance of the resist pattern such as mechanical strength, adhesion force between resist and substrate, it is considered effective for improvement of pattern collapse to control resist film properties by track process, i.e., optimization of the mechanical properties of the resist film and enhancement of the adhesion force between resist and substrate3) -5). In this study, we focused on the mechanical strength of the resist film and examined how post applied bake (PAB) condition affects the pattern collapse behavior. From ellipsometry measurement, it was found that increasing PAB time and temperature resulted in thickness reduction and refractive index increase, which suggested that the density of the resist film became high. Then we analyzed the mechanical strength of the resist film with the tip indentation method using atomic force microscope. It was found that the hardness of the resist film was affected by PAB conditions and regardless of PAB condition, hardened layer existed beneath the film surface. Finally, we carried out the measurements of loads to collapse 180nm resist dot patterns using the direct peeling with atomic force microscope tip (DPAT) method. Loads ranged from 600 to 2000nN overall and essentially increased as seen for indentation measurements when PAB temperature or time was increased, except some critical conditions. Through these evaluations using AFM, we succeeded in quantitatively evaluate the mechanical properties of the resist films processed with various PAB conditions. It was found that PAB condition obviously impacts on the hardness of the resist film and it is closely related to pattern collapse load.
It is necessary to develop a nano-bubble detector similar as a conventional particle counter for reducing micro and nano defects caused by nano-bubble (NB) in immersion lithography. In this regard, we discuss adhesion and removal mechanisms of NB adhered on a resist surface for immersion lithography. The micro and nano bubbles are more likely to adhere to the micro defect on the resist surface and lens surface. Keeping cleanness of lens and resist surface is necessary in order to prevent the micro bubble adhesion. We employed the AFM (Atomic Force Microscope) for the observation of NBs on a Si substrate and a resist surface. The diameter and height of NBs observed are approximately 40~100nm and 3~8nm, respectively. By approaching the AFM tip onto the NBs, the repulsive force can be detected but the attractive force on the resist surface. The interaction analysis between the AFM tip and the ArF excimer resist surface is effective in order to identify the NBs and to distinguish from solid particles. These phenomena can be discussed on the basis of Lifshitz theory. The separation procedure of the NB is accomplished with the AFM tip. The applying load at which the NB can be separated into the minute one is approximately 5nN. In addition, by the thermodynamic analysis, it can be considered that the NB adhered on the resist surface tends to be a flat shape and spread on the resist surface. It is difficult to adhere the bubbles on the resist surface.
One key challenge in sub-100 nm lithography is line pattern collapse. Pattern collapse has become an obstacle in device manufacturing processes requiring dense-high aspect ratio resist lines. In addition to pattern collapse, defect control continues to be a factor in IC manufacturing. In this study, the impact of a formulated surface conditioner, OptiPatten® Clear, with bifunctional capabilities: improved non-collapse window and defect control, was tested using a 193 nm lithographic process. To determine pattern collapse performance, 100 nm dense lines/space (L/S) and 100 nm 1:0.9 L/S were patterned into 240 nm of resist on 200 mm wafers. The wafers were then processed with developer and a formulated surface conditioner and compared to wafers processed with developer and DI water. When analyzed, wafers processed with surface conditioner had a 33% increase in Depth-of-Focus (DOF) and a 25% increase in Critical Normalized Aspect Ratio (CNAR) compared to DI water. Optical proximity effects are often credited for having a first-order influence on pattern collapse. Trench feature data was generated using an Scanning Electron Microscope (SEM) to compare the pattern collapse performance of OptiPattern Clear to DI water. The data strongly suggests optical proximity effects are a second-order factor which OptiPattern® Clear resolves. Defect performance for OptiPattern Clear was measured by comparison with a DI water baseline. A production reticle was used to process wafers patterned with 120 nm L/S with 240 nm of resist. The wafers processed with OptiPattern® Clear had similar defect performance as the DI water.
The micro bubbles condense in the concave channel and are trapped at the channel corner. In the experiments, the deionized (DI) water is dropped on a dry film resist (DFR) pattern. In the result, the micro bubble condensed and trapped at the different position in various shape patterns. The removal of micro bubbles adhered on a resist pattern has been recognized as one important factor in micro device manufacturing. We explained the condensation behavior of the micro bubble based on thermodynamics. The force acting on the bubble is estimated based on the force balance model between buoyancy and line tension. We can control and predict the micro bubble condensation by designing micro pattern arrangement.
In immersion lithography technique, some defects such as a watermark and a nanoscale bubble have been focused as the serious problems to be solved. In order to clarify the formation mechanism of the watermark, the in-situ observation of the drying behavior of the water drop containing the particles and without the particles, are conducted on the Si substrates. In the static watermark formation on the flat substrate, we can classify the watermark formation processes based on the watermark shapes. From the surface energy balance analysis, the particles dispersed in the DI-water adhere on the Si substrate. In addition, from the Laplace force balance, the particles adhered on the Si substrate will attract the surrounding particles. Hence, we can clarify the formation mechanism of the static watermark condensed in the ring shape. Meanwhile, in the dynamic watermark formation, we can observe clearly the condensed watermark is formed on the Si substrate and the particles move to lower region in inclined drop. In actual immersion lithography system, we can discuss the particles are more likely to remain in the immersion liquid under the lens system.
Various sizes of concave square patterns are used for microscale bubble adhesion and removal investigation in a water/methanol mixture solution. As decreasing the surface energy of the solution, the micro bubbles are more likely to remove from the square patterns. However, the micro bubble is less likely to remove as decreasing the square size of patterns. The threshold concentration of water/methanol solution for bubble removal can be determined experimentally. Based on the surface energy analysis, the adhesion and removal mechanisms of micro bubble can be explained. The nanoscale bubbles adhered on an ArF excimer resist surface can be observed clearly by using atomic force microscope (AFM). The growth of bubbles on the ArF excimer resist surface can be imaged. By the AFM technique, nanoscale bubble can be divided into some minute bubbles on the ArF resist surface under applying certain force about 5nN. The condensation nature of nanoscale bubbles is discussed.
Recently, importance of reducing the post development defects is being emphasized. There are a lot of countermeasures to reduce the defects. However, most of them are quite costly or require complicated process systems. In our previous report, it was found that short develop time process is effective to reduce micro bridge defects for a 193 nm resist, although the mechanism of this phenomenon was unclear. In this study, we focused on the properties of a 193 nm resist during the development process for the purpose of finding the mechanism of defect reduction by short develop time process. We first evaluated the effect of “exposure dose” and “developing time”; two parameters which were inevitably changed in short develop time process. Our original defect evaluation method was employed for this purpose. Evaluation results indicated that increased exposure dose to optimize critical dimension (CD) in short develop time process has a larger impact on defectivity than shortening developing time itself. Infrared (IR) spectroscopy study of the resist film revealed that there was a good correlation between defectivity and deprotection ratio of the resist polymer, which suggested that polarity of the resist was a key to control defectivity. Finally, impact of resist polarity on defectivity was confirmed by changing the polarity of the rinse solution. Based on these experimental results, we proposed the mechanism of development defect improvement by short develop time process.
Adhesion property of resist is characterized with DPAT (direct peeling with atomic force microscope (AFM) tip) method using 193 nm resist patterns of 180 nm dot shape which were developed for various developing time between 12 and 120 seconds in order to analyze the phenomenon which the short develop time process had led to suppress the pattern collapse. Surface free energy and refractive index of resist film treated with the developing time were also investigated from a thermodynamic point of view. The balance model among surface energy was adopted for analyzing intrusion phenomenon of developer solution into the resist-substrate interface. It can be explained quantitatively that the intrusion energy of developer solution acts to weaken the adhesion strength of resist pattern to the substrate. Furthermore, the intrusion energy became larger with increasing developing time. Analysis with the DPAT method indicates that the pattern collapse occurs accompanied with interface and cohesion destruction. Interface-scientifically speaking, the short develop time process proved to be effective to suppress the pattern collapse because of higher adhesion energy of the resist pattern to the substrate in shorter developing time.
Mechanical strength of resist film processed by various post apply bake (PAB) conditions were measured utilizing the tip indentation method using atomic force microscope (AFM). With the tip indentation method, we could quantify mechanical strength of resist film in terms of “degree of softening.” It was found that PAB at our standard baking temperature tends to lead to softening of the resist film which is considered due to existence of softening point of the resist polymer. Also changing baking time at this temperature showed very complicated softness behavior. By control of baking temperature, we could obtain harder resist film as baking time becomes longer. Further analysis of these resist film properties by ellipsometry suggested that changes in mechanical strength occur by the evaporation of the resist solvent and/or structure changes inside the resist film, depending upon baking conditions.
A short develop time process was investigated and assessed in terms of various pattern features of a resist. Process latitude for a positive DUV resist was evaluated for various pitches of line-and-space patterns and contact hole patterns for different develop times. It was found that the process latitude, depth of focus (DOF) and exposure latitude (EL) were improved by shortening develop time for various pattern features. The characteristics of CD variation to develop time for each pattern feature agree with the suggestion in our previous paper that expanding resist process latitude was strongly correlated with the resist develop rate and that terminating the develop reaction while the resist develop rate remained large was the key to expanding the process latitude. The short develop time process contributed to the larger γ characteristics of the resist, a smaller thickness loss and also a lesser degree of surface roughness in the resist pattern, which led to an appropriate resist pattern for the semiconductor process. A novel develop application system was developed by considering the loci of movements of Dainippon Screen’s (DNS) slit-scan develop nozzle and a rinse nozzle on the wafer. It was found that the novel develop application system achieved highly accurate CD controllability while realizing the benefits of the short develop time process.
Short develop time process was intensely investigated and characterized. Process margin for two different 193nm chemically amplified positive resists were analyzed for different develop times. It was found that the process margin, Exposure Latitude(EL) and Depth of Focus (DOF) for both resists is increased by shortened develop time. Resist develop rate and pattern wall angle characterization revealed that an improvement in process margin is strongly correlated to the resist develop rate and the key to obtain increased process margin is to terminate the develop reaction while the resist dissolution rate remains large. The “short develop time” benefits are suggested to result from the reduced dependence of the developed pattern on the latent image due to incomplete develop caused by the early termination of the develop reaction. Deeper investigation revealed the resist develop rate was affected by the develop application method as well as resist chemical differences. Dainippon Screen’s (DNS) slit-scan develop system is revealed to be very effective in controlling the resist develop rate because of its ability to apply the developer puddle very still and suitable for the short develop time process. It was also confirmed that the pattern collapse was reduced by shortening develop time. It is suggested this phenomenon is correlated to the penetration of developer into the resist-substrate interface as well as the change in pattern wall angle as a function of develop time. Post-develop defect levels have been confirmed for one 193nm resist over a range different develop times. This study revealed that develop time shortening resulted in fewer develop defects. In summary it is confirmed that short develop time process has the advantages of improved process margin for factors such as EL, DOF, pattern collapse, develop defects as well as throughput.
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