An efficient parallel architecture design for the iris unwrapping process in a real-time iris recognition system using the
Bresenham Circle Algorithm is presented in this paper. Based on the characteristics of the model parameters this
algorithm was chosen over the widely used polar conversion technique as the iris unwrapping model. The architecture
design is parallelized to increase the throughput of the system and is suitable for processing an inputted image size of
320 × 240 pixels in real-time using Field Programmable Gate Array (FPGA) technology. Quartus software is used to
implement, verify, and analyze the design’s performance using the VHSIC Hardware Description Language. The
system’s predicted processing time is faster than the modern iris unwrapping technique used today∗.
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